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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-vsr-nums-as-vr \3; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s4; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu -ppc-vsr-nums-as-vr \5; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=CHECK-BE6 7@Globi = external global i32, align 48@Globf = external global float, align 49 10define <2 x i64> @test1(i64 %a, i64 %b) {11; CHECK-LABEL: test1:12; CHECK: # %bb.0: # %entry13; CHECK-NEXT: mtvsrdd v2, r4, r314; CHECK-NEXT: blr15;16; CHECK-BE-LABEL: test1:17; CHECK-BE: # %bb.0: # %entry18; CHECK-BE-NEXT: mtvsrdd v2, r3, r419; CHECK-BE-NEXT: blr20 21entry:22; The FIXME below is due to the lowering for BUILD_VECTOR needing a re-vamp23; which will happen in a subsequent patch.24 %vecins = insertelement <2 x i64> undef, i64 %a, i32 025 %vecins1 = insertelement <2 x i64> %vecins, i64 %b, i32 126 ret <2 x i64> %vecins127}28 29define i64 @test2(<2 x i64> %a) {30; CHECK-LABEL: test2:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: mfvsrld r3, v233; CHECK-NEXT: blr34;35; CHECK-BE-LABEL: test2:36; CHECK-BE: # %bb.0: # %entry37; CHECK-BE-NEXT: mfvsrd r3, v238; CHECK-BE-NEXT: blr39 40entry:41 %0 = extractelement <2 x i64> %a, i32 042 ret i64 %043}44 45define i64 @test3(<2 x i64> %a) {46; CHECK-LABEL: test3:47; CHECK: # %bb.0: # %entry48; CHECK-NEXT: mfvsrd r3, v249; CHECK-NEXT: blr50;51; CHECK-BE-LABEL: test3:52; CHECK-BE: # %bb.0: # %entry53; CHECK-BE-NEXT: mfvsrld r3, v254; CHECK-BE-NEXT: blr55 56entry:57 %0 = extractelement <2 x i64> %a, i32 158 ret i64 %059}60 61define <4 x i32> @test4(ptr nocapture readonly %in) {62; CHECK-LABEL: test4:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: lxvwsx v2, 0, r365; CHECK-NEXT: blr66;67; CHECK-BE-LABEL: test4:68; CHECK-BE: # %bb.0: # %entry69; CHECK-BE-NEXT: lxvwsx v2, 0, r370; CHECK-BE-NEXT: blr71 72entry:73 %0 = load i32, ptr %in, align 474 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 075 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer76 ret <4 x i32> %splat.splat77}78 79define <4 x float> @test5(ptr nocapture readonly %in) {80; CHECK-LABEL: test5:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: lxvwsx v2, 0, r383; CHECK-NEXT: blr84;85; CHECK-BE-LABEL: test5:86; CHECK-BE: # %bb.0: # %entry87; CHECK-BE-NEXT: lxvwsx v2, 0, r388; CHECK-BE-NEXT: blr89 90entry:91 %0 = load float, ptr %in, align 492 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 093 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer94 ret <4 x float> %splat.splat95}96 97define <4 x i32> @test6() {98; CHECK-LABEL: test6:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: addis r3, r2, .LC0@toc@ha101; CHECK-NEXT: ld r3, .LC0@toc@l(r3)102; CHECK-NEXT: lxvwsx v2, 0, r3103; CHECK-NEXT: blr104;105; CHECK-BE-LABEL: test6:106; CHECK-BE: # %bb.0: # %entry107; CHECK-BE-NEXT: addis r3, r2, .LC0@toc@ha108; CHECK-BE-NEXT: ld r3, .LC0@toc@l(r3)109; CHECK-BE-NEXT: lxvwsx v2, 0, r3110; CHECK-BE-NEXT: blr111 112entry:113 %0 = load i32, ptr @Globi, align 4114 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0115 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer116 ret <4 x i32> %splat.splat117}118 119define <4 x float> @test7() {120; CHECK-LABEL: test7:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: addis r3, r2, .LC1@toc@ha123; CHECK-NEXT: ld r3, .LC1@toc@l(r3)124; CHECK-NEXT: lxvwsx v2, 0, r3125; CHECK-NEXT: blr126;127; CHECK-BE-LABEL: test7:128; CHECK-BE: # %bb.0: # %entry129; CHECK-BE-NEXT: addis r3, r2, .LC1@toc@ha130; CHECK-BE-NEXT: ld r3, .LC1@toc@l(r3)131; CHECK-BE-NEXT: lxvwsx v2, 0, r3132; CHECK-BE-NEXT: blr133 134entry:135 %0 = load float, ptr @Globf, align 4136 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0137 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer138 ret <4 x float> %splat.splat139}140 141define <16 x i8> @test8() {142; CHECK-LABEL: test8:143; CHECK: # %bb.0: # %entry144; CHECK-NEXT: xxlxor v2, v2, v2145; CHECK-NEXT: blr146;147; CHECK-BE-LABEL: test8:148; CHECK-BE: # %bb.0: # %entry149; CHECK-BE-NEXT: xxlxor v2, v2, v2150; CHECK-BE-NEXT: blr151 152entry:153 ret <16 x i8> zeroinitializer154}155 156define <16 x i8> @test9() {157; CHECK-LABEL: test9:158; CHECK: # %bb.0: # %entry159; CHECK-NEXT: xxspltib v2, 1160; CHECK-NEXT: blr161;162; CHECK-BE-LABEL: test9:163; CHECK-BE: # %bb.0: # %entry164; CHECK-BE-NEXT: xxspltib v2, 1165; CHECK-BE-NEXT: blr166 167entry:168 ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>169}170 171define <16 x i8> @test10() {172; CHECK-LABEL: test10:173; CHECK: # %bb.0: # %entry174; CHECK-NEXT: xxspltib v2, 127175; CHECK-NEXT: blr176;177; CHECK-BE-LABEL: test10:178; CHECK-BE: # %bb.0: # %entry179; CHECK-BE-NEXT: xxspltib v2, 127180; CHECK-BE-NEXT: blr181 182entry:183 ret <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>184}185 186define <16 x i8> @test11() {187; CHECK-LABEL: test11:188; CHECK: # %bb.0: # %entry189; CHECK-NEXT: xxspltib v2, 128190; CHECK-NEXT: blr191;192; CHECK-BE-LABEL: test11:193; CHECK-BE: # %bb.0: # %entry194; CHECK-BE-NEXT: xxspltib v2, 128195; CHECK-BE-NEXT: blr196 197entry:198 ret <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>199}200 201define <16 x i8> @test12() {202; CHECK-LABEL: test12:203; CHECK: # %bb.0: # %entry204; CHECK-NEXT: xxleqv v2, v2, v2205; CHECK-NEXT: blr206;207; CHECK-BE-LABEL: test12:208; CHECK-BE: # %bb.0: # %entry209; CHECK-BE-NEXT: xxleqv v2, v2, v2210; CHECK-BE-NEXT: blr211 212entry:213 ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>214}215 216define <16 x i8> @test13() {217; CHECK-LABEL: test13:218; CHECK: # %bb.0: # %entry219; CHECK-NEXT: xxspltib v2, 129220; CHECK-NEXT: blr221;222; CHECK-BE-LABEL: test13:223; CHECK-BE: # %bb.0: # %entry224; CHECK-BE-NEXT: xxspltib v2, 129225; CHECK-BE-NEXT: blr226 227entry:228 ret <16 x i8> <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127>229}230 231define <16 x i8> @test13E127() {232; CHECK-LABEL: test13E127:233; CHECK: # %bb.0: # %entry234; CHECK-NEXT: xxspltib v2, 200235; CHECK-NEXT: blr236;237; CHECK-BE-LABEL: test13E127:238; CHECK-BE: # %bb.0: # %entry239; CHECK-BE-NEXT: xxspltib v2, 200240; CHECK-BE-NEXT: blr241 242entry:243 ret <16 x i8> <i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200>244}245 246define <4 x i32> @test14(<4 x i32> %a, ptr nocapture readonly %b) {247; CHECK-LABEL: test14:248; CHECK: # %bb.0: # %entry249; CHECK-NEXT: lwz r3, 0(r5)250; CHECK-NEXT: mtfprwz f0, r3251; CHECK-NEXT: addi r3, r3, 5252; CHECK-NEXT: xxspltw v2, vs0, 1253; CHECK-NEXT: stw r3, 0(r5)254; CHECK-NEXT: blr255;256; CHECK-BE-LABEL: test14:257; CHECK-BE: # %bb.0: # %entry258; CHECK-BE-NEXT: lwz r3, 0(r5)259; CHECK-BE-NEXT: mtfprwz f0, r3260; CHECK-BE-NEXT: addi r3, r3, 5261; CHECK-BE-NEXT: xxspltw v2, vs0, 1262; CHECK-BE-NEXT: stw r3, 0(r5)263; CHECK-BE-NEXT: blr264 265entry:266 %0 = load i32, ptr %b, align 4267 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0268 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer269 %1 = add i32 %0, 5270 store i32 %1, ptr %b, align 4271 ret <4 x i32> %splat.splat272}273