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1; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-64,ENABLE-642; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-64,DISABLE-643; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -mattr=-altivec -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-32,ENABLE-324; RUN: llc -mtriple=powerpc-ibm-aix-xcoff %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-32,DISABLE-325; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -mattr=-altivec -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-64,ENABLE-646; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-64,DISABLE-64,DISABLE-64-AIX7;8;9; Note: Lots of tests use inline asm instead of regular calls.10; This allows to have a better control on what the allocation will do.11; Otherwise, we may have spill right in the entry block, defeating12; shrink-wrapping. Moreover, some of the inline asm statement (nop)13; are here to ensure that the related paths do not end up as critical14; edges.15 16 17; Initial motivating example: Simple diamond with a call just on one side.18; CHECK-LABEL: {{.*}}foo:19;20; Compare the arguments and return21; No prologue needed.22; ENABLE: cmpw 3, 423; ENABLE-NEXT: bgelr 024;25; Prologue code.26; At a minimum, we save/restore the link register. Other registers may be saved27; as well.28; CHECK: mflr29;30; Compare the arguments and jump to exit.31; After the prologue is set.32; DISABLE: cmpw 3, 433; DISABLE-32: stw 0,34; DISABLE-64-AIX: std 0,35; DISABLE-NEXT: bge 0, {{.*}}[[EXIT_LABEL:BB[0-9_]+]]36;37; Store %a on the stack38; CHECK: stw 3, {{[0-9]+([0-9]+)}}39; Set the alloca address in the second argument.40; CHECK-NEXT: addi 4, 1, {{[0-9]+}}41; Set the first argument to zero.42; CHECK-NEXT: li 3, 043; CHECK-NEXT: bl {{.*}}doSomething44;45; With shrink-wrapping, epilogue is just after the call.46; Restore the link register and return.47; Note that there could be other epilog code before the link register is48; restored but we will not check for it here.49; ENABLE: mtlr50; ENABLE-NEXT: blr51;52; DISABLE: [[EXIT_LABEL]]:53;54; Without shrink-wrapping, epilogue is in the exit block.55; Epilogue code. (What we pop does not matter.)56; DISABLE: mtlr {{[0-9]+}}57; DISABLE-NEXT: blr58;59 60define i32 @foo(i32 %a, i32 %b) {61 %tmp = alloca i32, align 462 %tmp2 = icmp slt i32 %a, %b63 br i1 %tmp2, label %true, label %false64 65true:66 store i32 %a, ptr %tmp, align 467 %tmp4 = call i32 @doSomething(i32 0, ptr %tmp)68 br label %false69 70false:71 %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]72 ret i32 %tmp.073}74 75; Function Attrs: optsize76declare i32 @doSomething(i32, ptr)77 78 79; Check that we do not perform the restore inside the loop whereas the save80; is outside.81; CHECK-LABEL: {{.*}}freqSaveAndRestoreOutsideLoop:82;83; Shrink-wrapping allows to skip the prologue in the else case.84; ENABLE: cmplwi 3, 085; ENABLE: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]86;87; Prologue code.88; Make sure we save the link register89; CHECK: mflr {{[0-9]+}}90;91; DISABLE: cmplwi 3, 092; DISABLE: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]93;94; Loop preheader95; CHECK-DAG: li [[SUM:[0-9]+]], 096; CHECK-DAG: li [[IV:[0-9]+]], 1097;98; Loop body99; CHECK: {{.*}}[[LOOP:BB[0-9_]+]]: # %for.body100; CHECK: bl {{.*}}something101;102; CHECK-64-DAG: addi [[IV]], [[IV]], -1103; CHECK-64-DAG: add [[SUM]], 3, [[SUM]]104; CHECK-64-DAG: cmpldi [[IV]], 0105; CHECK-32-DAG: addi [[IV]], [[IV]], -1106; CHECK-32-DAG: add [[SUM]], 3, [[SUM]]107; CHECK-32-DAG: cmplwi [[IV]], 0108; CHECK-NEXT: bc 12, 1, {{.*}}[[LOOP]]109;110; Next BB.111; CHECK: slwi 3, [[SUM]], 3112;113; Jump to epilogue.114; DISABLE: b {{.*}}[[EPILOG_BB:BB[0-9_]+]]115;116; DISABLE: {{.*}}[[ELSE_LABEL]]: # %if.else117; Shift second argument by one and store into returned register.118; DISABLE: slwi 3, 4, 1119; DISABLE: {{.*}}[[EPILOG_BB]]: # %if.end120;121; Epilogue code.122; CHECK: mtlr {{[0-9]+}}123; CHECK: blr124;125; ENABLE: {{.*}}[[ELSE_LABEL]]: # %if.else126; Shift second argument by one and store into returned register.127; ENABLE: slwi 3, 4, 1128; ENABLE-NEXT: blr129define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {130entry:131 %tobool = icmp eq i32 %cond, 0132 br i1 %tobool, label %if.else, label %for.preheader133 134for.preheader:135 tail call void asm "nop", ""()136 br label %for.body137 138for.body: ; preds = %entry, %for.body139 %i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]140 %sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]141 %call = tail call i32 @something()142 %add = add nsw i32 %call, %sum.04143 %inc = add nuw nsw i32 %i.05, 1144 %exitcond = icmp eq i32 %inc, 10145 br i1 %exitcond, label %for.end, label %for.body146 147for.end: ; preds = %for.body148 %shl = shl i32 %add, 3149 br label %if.end150 151if.else: ; preds = %entry152 %mul = shl nsw i32 %N, 1153 br label %if.end154 155if.end: ; preds = %if.else, %for.end156 %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]157 ret i32 %sum.1158}159 160declare i32 @something(...)161 162; Check that we do not perform the shrink-wrapping inside the loop even163; though that would be legal. The cost model must prevent that.164; CHECK-LABEL: {{.*}}freqSaveAndRestoreOutsideLoop2:165; Prologue code.166; Make sure we save the link register before the call167; CHECK: mflr {{[0-9]+}}168;169; Loop preheader170; CHECK-DAG: li [[SUM:[0-9]+]], 0171; CHECK-DAG: li [[IV:[0-9]+]], 10172;173; Loop body174; CHECK: {{.*}}[[LOOP:BB[0-9_]+]]: # %for.body175; CHECK: bl {{.*}}something176;177; CHECK-64-DAG: addi [[IV]], [[IV]], -1178; CHECK-64-DAG: add [[SUM]], 3, [[SUM]]179; CHECK-64-DAG: cmpldi [[IV]], 0180; CHECK-32-DAG: addi [[IV]], [[IV]], -1181; CHECK-32-DAG: add [[SUM]], 3, [[SUM]]182; CHECK-32-DAG: cmplwi [[IV]], 0183;184; CHECK-NEXT: bc 12, 1, {{.*}}[[LOOP]]185;186; Next BB187; CHECK: %for.exit188; CHECK: mtlr {{[0-9]+}}189; CHECK: blr190define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {191entry:192 br label %for.preheader193 194for.preheader:195 tail call void asm "nop", ""()196 br label %for.body197 198for.body: ; preds = %for.body, %entry199 %i.04 = phi i32 [ 0, %for.preheader ], [ %inc, %for.body ]200 %sum.03 = phi i32 [ 0, %for.preheader ], [ %add, %for.body ]201 %call = tail call i32 @something()202 %add = add nsw i32 %call, %sum.03203 %inc = add nuw nsw i32 %i.04, 1204 %exitcond = icmp eq i32 %inc, 10205 br i1 %exitcond, label %for.exit, label %for.body206 207for.exit:208 tail call void asm "nop", ""()209 br label %for.end210 211for.end: ; preds = %for.body212 ret i32 %add213}214 215 216; Check with a more complex case that we do not have save within the loop and217; restore outside.218; CHECK-LABEL: {{.*}}loopInfoSaveOutsideLoop:219;220; ENABLE: cmplwi 3, 0221; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]222;223; Prologue code.224; Make sure we save the link register225; CHECK: mflr {{[0-9]+}}226;227; DISABLE-64-DAG: std {{[0-9]+}}228; DISABLE-64-DAG: std {{[0-9]+}}229; DISABLE-64-DAG: std {{[0-9]+}}230; DISABLE-64-DAG: stdu 1,231; DISABLE-64-DAG: cmplwi 3, 0232;233; DISABLE-32-DAG: stw {{[0-9]+}}234; DISABLE-32-DAG: stw {{[0-9]+}}235; DISABLE-32-DAG: stw {{[0-9]+}}236; DISABLE-32-DAG: stwu 1,237; DISABLE-32-DAG: cmplwi 3, 0238;239; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]240;241; Loop preheader242; CHECK-DAG: li [[SUM:[0-9]+]], 0243; CHECK-DAG: li [[IV:[0-9]+]], 10244;245; Loop body246; CHECK: {{.*}}[[LOOP:BB[0-9_]+]]: # %for.body247; CHECK: bl {{.*}}something248;249; CHECK-64-DAG: addi [[IV]], [[IV]], -1250; CHECK-64-DAG: add [[SUM]], 3, [[SUM]]251; CHECK-64-DAG: cmpldi [[IV]], 0252; CHECK-32-DAG: addi [[IV]], [[IV]], -1253; CHECK-32-DAG: add [[SUM]], 3, [[SUM]]254; CHECK-32-DAG: cmplwi [[IV]], 0255;256; CHECK-NEXT: bc 12, 1, {{.*}}[[LOOP]]257;258; Next BB259; CHECK: bl {{.*}}somethingElse260; CHECK: slwi 3, [[SUM]], 3261;262; Jump to epilogue263; DISABLE: b {{.*}}[[EPILOG_BB:BB[0-9_]+]]264;265; DISABLE: {{.*}}[[ELSE_LABEL]]: # %if.else266; Shift second argument by one and store into returned register.267; DISABLE: slwi 3, 4, 1268;269; DISABLE: {{.*}}[[EPILOG_BB]]: # %if.end270;271; Epilog code272; CHECK: mtlr {{[0-9]+}}273; CHECK: blr274;275; ENABLE: {{.*}}[[ELSE_LABEL]]: # %if.else276; Shift second argument by one and store into returned register.277; ENABLE: slwi 3, 4, 1278; ENABLE-NEXT: blr279define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {280entry:281 %tobool = icmp eq i32 %cond, 0282 br i1 %tobool, label %if.else, label %for.preheader283 284for.preheader:285 tail call void asm "nop", ""()286 br label %for.body287 288for.body: ; preds = %entry, %for.body289 %i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]290 %sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]291 %call = tail call i32 @something()292 %add = add nsw i32 %call, %sum.04293 %inc = add nuw nsw i32 %i.05, 1294 %exitcond = icmp eq i32 %inc, 10295 br i1 %exitcond, label %for.end, label %for.body296 297for.end: ; preds = %for.body298 tail call void @somethingElse()299 %shl = shl i32 %add, 3300 br label %if.end301 302if.else: ; preds = %entry303 %mul = shl nsw i32 %N, 1304 br label %if.end305 306if.end: ; preds = %if.else, %for.end307 %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]308 ret i32 %sum.1309}310 311declare void @somethingElse(...)312 313; Check with a more complex case that we do not have restore within the loop and314; save outside.315; CHECK-LABEL: {{.*}}loopInfoRestoreOutsideLoop:316;317; ENABLE: cmplwi 3, 0318; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]319;320; Prologue code.321; Make sure we save the link register322; CHECK: mflr {{[0-9]+}}323;324; DISABLE-64-DAG: std {{[0-9]+}}325; DISABLE-64-DAG: std {{[0-9]+}}326; DISABLE-64-DAG: std {{[0-9]+}}327; DISABLE-64-DAG: stdu 1,328; DISABLE-64-DAG: cmplwi 3, 0329;330; DISABLE-32-DAG: stw {{[0-9]+}}331; DISABLE-32-DAG: stw {{[0-9]+}}332; DISABLE-32-DAG: stw {{[0-9]+}}333; DISABLE-32-DAG: stwu 1,334; DISABLE-32-DAG: cmplwi 3, 0335;336; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]337;338; CHECK: bl {{.*}}somethingElse339;340; Loop preheader341; CHECK-DAG: li [[SUM:[0-9]+]], 0342; CHECK-DAG: li [[IV:[0-9]+]], 10343;344; Loop body345; CHECK: {{.*}}[[LOOP:BB[0-9_]+]]: # %for.body346; CHECK: bl {{.*}}something347;348; CHECK-64-DAG: addi [[IV]], [[IV]], -1349; CHECK-64-DAG: add [[SUM]], 3, [[SUM]]350; CHECK-64-DAG: cmpldi [[IV]], 0351; CHECK-32-DAG: addi [[IV]], [[IV]], -1352; CHECK-32-DAG: add [[SUM]], 3, [[SUM]]353; CHECK-32-DAG: cmplwi [[IV]], 0354;355; CHECK-NEXT: bc 12, 1, {{.*}}[[LOOP]]356;357; Next BB.358; CHECK: slwi 3, [[SUM]], 3359;360; DISABLE: b {{.*}}[[EPILOG_BB:BB[0-9_]+]]361;362; DISABLE: {{.*}}[[ELSE_LABEL]]: # %if.else363; Shift second argument by one and store into returned register.364; DISABLE: slwi 3, 4, 1365; DISABLE: {{.*}}[[EPILOG_BB]]: # %if.end366;367; Epilogue code.368; CHECK: mtlr {{[0-9]+}}369; CHECK: blr370;371; ENABLE: {{.*}}[[ELSE_LABEL]]: # %if.else372; Shift second argument by one and store into returned register.373; ENABLE: slwi 3, 4, 1374; ENABLE-NEXT: blr375define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) nounwind {376entry:377 %tobool = icmp eq i32 %cond, 0378 br i1 %tobool, label %if.else, label %if.then379 380if.then: ; preds = %entry381 tail call void @somethingElse()382 br label %for.body383 384for.body: ; preds = %for.body, %if.then385 %i.05 = phi i32 [ 0, %if.then ], [ %inc, %for.body ]386 %sum.04 = phi i32 [ 0, %if.then ], [ %add, %for.body ]387 %call = tail call i32 @something()388 %add = add nsw i32 %call, %sum.04389 %inc = add nuw nsw i32 %i.05, 1390 %exitcond = icmp eq i32 %inc, 10391 br i1 %exitcond, label %for.end, label %for.body392 393for.end: ; preds = %for.body394 %shl = shl i32 %add, 3395 br label %if.end396 397if.else: ; preds = %entry398 %mul = shl nsw i32 %N, 1399 br label %if.end400 401if.end: ; preds = %if.else, %for.end402 %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]403 ret i32 %sum.1404}405 406; Check that we handle function with no frame information correctly.407; CHECK-LABEL: {{.*}}emptyFrame:408; CHECK: # %entry409; CHECK-NEXT: li 3, 0410; CHECK-NEXT: blr411define i32 @emptyFrame() {412entry:413 ret i32 0414}415 416 417; Check that we handle inline asm correctly.418; CHECK-LABEL: {{.*}}inlineAsm:419;420; ENABLE: cmplwi 3, 0421; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]422;423; Prologue code.424; Make sure we save the CSR used in the inline asm: r31425; ENABLE-DAG: li [[IV:[0-9]+]], 10426; ENABLE-64-DAG: std 31, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill427; ENABLE-32-DAG: stw 31, -[[STACK_OFFSET:[0-9]+]](1) # 4-byte Folded Spill428;429; DISABLE: cmplwi 3, 0430; DISABLE-64-NEXT: std 31, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill431; DISABLE-32-NEXT: stw 31, -[[STACK_OFFSET:[0-9]+]](1) # 4-byte Folded Spill432; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]433; DISABLE: li [[IV:[0-9]+]], 10434;435; CHECK: nop436; CHECK: mtctr [[IV]]437;438; CHECK: {{.*}}[[LOOP_LABEL:BB[0-9_]+]]: # %for.body439; Inline asm statement.440; CHECK: addi 31, 14, 1441; CHECK: bdnz {{.*}}[[LOOP_LABEL]]442;443; Epilogue code.444; CHECK: li 3, 0445; CHECK-64-DAG: ld 31, -[[STACK_OFFSET]](1) # 8-byte Folded Reload446; CHECK-32-DAG: lwz 31, -[[STACK_OFFSET]](1) # 4-byte Folded Reload447; CHECK-DAG: nop448; CHECK: blr449;450; CHECK: [[ELSE_LABEL]]451; CHECK-NEXT: slwi 3, 4, 1452; DISABLE-64-NEXT: ld 31, -[[STACK_OFFSET]](1) # 8-byte Folded Reload453; DISABLE-32-NEXT: lwz 31, -[[STACK_OFFSET]](1) # 4-byte Folded Reload454; CHECK-NEXT: blr455define i32 @inlineAsm(i32 %cond, i32 %N) {456entry:457 %tobool = icmp eq i32 %cond, 0458 br i1 %tobool, label %if.else, label %for.preheader459 460for.preheader:461 tail call void asm "nop", ""()462 br label %for.body463 464for.body: ; preds = %entry, %for.body465 %i.03 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]466 tail call void asm "addi 31, 14, 1", "~{r31}"()467 %inc = add nuw nsw i32 %i.03, 1468 %exitcond = icmp eq i32 %inc, 10469 br i1 %exitcond, label %for.exit, label %for.body470 471for.exit:472 tail call void asm "nop", ""()473 br label %if.end474 475if.else: ; preds = %entry476 %mul = shl nsw i32 %N, 1477 br label %if.end478 479if.end: ; preds = %for.body, %if.else480 %sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ]481 ret i32 %sum.0482}483 484 485; Check that we handle calls to variadic functions correctly.486; CHECK-LABEL: {{.*}}callVariadicFunc:487;488; ENABLE: cmplwi 3, 0489; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]490;491; Prologue code.492; CHECK: mflr {{[0-9]+}}493;494; DISABLE: cmplwi 3, 0495; DISABLE-32: stw 0, 72(1)496; DISABLE-64-AIX: std 0,497; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]498;499; Setup of the varags.500; CHECK-64: mr 4, 3501; CHECK-64-NEXT: mr 5, 3502; CHECK-64-NEXT: mr 6, 3503; CHECK-64-NEXT: mr 7, 3504; CHECK-64-NEXT: mr 8, 3505; CHECK-64-NEXT: mr 9, 3506;507; CHECK-32: mr 3, 4508; CHECK-32-NEXT: mr 5, 4509; ENABLE-32-NEXT: stw 0, 72(1)510; CHECK-32: mr 6, 4511; CHECK-32-NEXT: mr 7, 4512; CHECK-32-NEXT: mr 8, 4513; CHECK-32-NEXT: mr 9, 4514;515; CHECK-NEXT: bl {{.*}}someVariadicFunc516; CHECK: slwi 3, 3, 3517; DISABLE: b {{.*}}[[EPILOGUE_BB:BB[0-9_]+]]518;519; ENABLE: mtlr {{[0-9]+}}520; ENABLE-NEXT: blr521;522; CHECK: {{.*}}[[ELSE_LABEL]]: # %if.else523; CHECK-NEXT: slwi 3, 4, 1524;525; DISABLE: {{.*}}[[EPILOGUE_BB]]: # %if.end526; DISABLE: mtlr527; CHECK: blr528define i32 @callVariadicFunc(i32 %cond, i32 %N) {529entry:530 %tobool = icmp eq i32 %cond, 0531 br i1 %tobool, label %if.else, label %if.then532 533if.then: ; preds = %entry534 %call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)535 %shl = shl i32 %call, 3536 br label %if.end537 538if.else: ; preds = %entry539 %mul = shl nsw i32 %N, 1540 br label %if.end541 542if.end: ; preds = %if.else, %if.then543 %sum.0 = phi i32 [ %shl, %if.then ], [ %mul, %if.else ]544 ret i32 %sum.0545}546 547declare i32 @someVariadicFunc(i32, ...)548 549 550 551; Make sure we do not insert unreachable code after noreturn function.552; Although this is not incorrect to insert such code, it is useless553; and it hurts the binary size.554;555; CHECK-LABEL: {{.*}}noreturn:556; DISABLE: mflr {{[0-9]+}}557;558; CHECK: cmplwi 3, 0559; DISABLE-32: stw 0, 72(1)560; DISABLE-64-AIX: std 0,561; CHECK-NEXT: bne{{[-]?}} 0, {{.*}}[[ABORT:BB[0-9_]+]]562;563; CHECK: li 3, 42564;565; DISABLE: mtlr {{[0-9]+}}566;567; CHECK-NEXT: blr568;569; CHECK: {{.*}}[[ABORT]]: # %if.abort570; ENABLE: mflr {{[0-9]+}}571; CHECK: bl {{.*}}abort572; ENABLE-NOT: mtlr {{[0-9]+}}573define i32 @noreturn(i8 signext %bad_thing) {574entry:575 %tobool = icmp eq i8 %bad_thing, 0576 br i1 %tobool, label %if.end, label %if.abort577 578if.abort:579 tail call void @abort() #0580 unreachable581 582if.end:583 ret i32 42584}585 586declare void @abort() #0587 588attributes #0 = { noreturn nounwind }589 590 591; Make sure that we handle infinite loops properly When checking that the Save592; and Restore blocks are control flow equivalent, the loop searches for the593; immediate (post) dominator for the (restore) save blocks. When either the Save594; or Restore block is located in an infinite loop the only immediate (post)595; dominator is itself. In this case, we cannot perform shrink wrapping, but we596; should return gracefully and continue compilation.597; The only condition for this test is the compilation finishes correctly.598;599; CHECK-LABEL: {{.*}}infiniteloop600; CHECK: blr601define void @infiniteloop() {602entry:603 br i1 undef, label %if.then, label %if.end604 605if.then:606 %ptr = alloca i32, i32 4607 br label %for.body608 609for.body: ; preds = %for.body, %entry610 %sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ]611 %call = tail call i32 @something()612 %add = add nsw i32 %call, %sum.03613 store i32 %add, ptr %ptr614 br label %for.body615 616if.end:617 ret void618}619 620; Another infinite loop test this time with a body bigger than just one block.621; CHECK-LABEL: {{.*}}infiniteloop2622; CHECK: blr623define void @infiniteloop2() {624entry:625 br i1 undef, label %if.then, label %if.end626 627if.then:628 %ptr = alloca i32, i32 4629 br label %for.body630 631for.body: ; preds = %for.body, %entry632 %sum.03 = phi i32 [ 0, %if.then ], [ %add, %body1 ], [ 1, %body2]633 %call = tail call i32 asm "mftb $0, 268", "=r,~{r14}"()634 %add = add nsw i32 %call, %sum.03635 store i32 %add, ptr %ptr636 br i1 undef, label %body1, label %body2637 638body1:639 tail call void asm sideeffect "nop", "~{r14}"()640 br label %for.body641 642body2:643 tail call void asm sideeffect "nop", "~{r14}"()644 br label %for.body645 646if.end:647 ret void648}649 650; Another infinite loop test this time with two nested infinite loop.651; CHECK-LABEL: {{.*}}infiniteloop3652; CHECK: bclr653define void @infiniteloop3() {654entry:655 br i1 undef, label %loop2a, label %body656 657body: ; preds = %entry658 br i1 undef, label %loop2a, label %end659 660loop1: ; preds = %loop2a, %loop2b661 %var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ]662 %next.phi = phi ptr [ %next.load, %loop2b ], [ %next.var, %loop2a ]663 %0 = icmp eq ptr %var, null664 %next.load = load ptr, ptr undef665 br i1 %0, label %loop2a, label %loop2b666 667loop2a: ; preds = %loop1, %body, %entry668 %var = phi ptr [ null, %body ], [ null, %entry ], [ %next.phi, %loop1 ]669 %next.var = phi ptr [ undef, %body ], [ null, %entry ], [ %next.load, %loop1 ]670 br label %loop1671 672loop2b: ; preds = %loop1673 store ptr %next.phi, ptr %var.phi674 br label %loop1675 676end:677 ret void678}679 680@columns = external global [0 x i32], align 4681@lock = common global i32 0, align 4682@htindex = common global i32 0, align 4683@stride = common global i32 0, align 4684@ht = common global ptr null, align 8685@he = common global ptr null, align 8686 687; Test for a bug that was caused when save point was equal to restore point.688; Function Attrs: nounwind689; CHECK-LABEL: {{.*}}transpose690;691; Store of callee-save register saved by shrink wrapping692; FIXME: Test disabled: Improved scheduling needs no spills/reloads any longer!693; CHECKXX: std [[CSR:[0-9]+]], -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill694;695; Reload of callee-save register696; CHECKXX: ld [[CSR]], -[[STACK_OFFSET]](1) # 8-byte Folded Reload697;698; Ensure no subsequent uses of callee-save register before end of function699; CHECKXX-NOT: {{[a-z]+}} [[CSR]]700; CHECK: blr701define signext i32 @transpose() {702entry:703 %0 = load i32, ptr getelementptr inbounds ([0 x i32], ptr @columns, i64 0, i64 1), align 4704 %shl.i = shl i32 %0, 7705 %1 = load i32, ptr getelementptr inbounds ([0 x i32], ptr @columns, i64 0, i64 2), align 4706 %or.i = or i32 %shl.i, %1707 %shl1.i = shl i32 %or.i, 7708 %2 = load i32, ptr getelementptr inbounds ([0 x i32], ptr @columns, i64 0, i64 3), align 4709 %or2.i = or i32 %shl1.i, %2710 %3 = load i32, ptr getelementptr inbounds ([0 x i32], ptr @columns, i64 0, i64 7), align 4711 %shl3.i = shl i32 %3, 7712 %4 = load i32, ptr getelementptr inbounds ([0 x i32], ptr @columns, i64 0, i64 6), align 4713 %or4.i = or i32 %shl3.i, %4714 %shl5.i = shl i32 %or4.i, 7715 %5 = load i32, ptr getelementptr inbounds ([0 x i32], ptr @columns, i64 0, i64 5), align 4716 %or6.i = or i32 %shl5.i, %5717 %cmp.i = icmp ugt i32 %or2.i, %or6.i718 br i1 %cmp.i, label %cond.true.i, label %cond.false.i719 720cond.true.i:721 %shl7.i = shl i32 %or2.i, 7722 %6 = load i32, ptr getelementptr inbounds ([0 x i32], ptr @columns, i64 0, i64 4), align 4723 %or8.i = or i32 %6, %shl7.i724 %conv.i = zext i32 %or8.i to i64725 %shl9.i = shl nuw nsw i64 %conv.i, 21726 %conv10.i = zext i32 %or6.i to i64727 %or11.i = or i64 %shl9.i, %conv10.i728 br label %hash.exit729 730cond.false.i:731 %shl12.i = shl i32 %or6.i, 7732 %7 = load i32, ptr getelementptr inbounds ([0 x i32], ptr @columns, i64 0, i64 4), align 4733 %or13.i = or i32 %7, %shl12.i734 %conv14.i = zext i32 %or13.i to i64735 %shl15.i = shl nuw nsw i64 %conv14.i, 21736 %conv16.i = zext i32 %or2.i to i64737 %or17.i = or i64 %shl15.i, %conv16.i738 br label %hash.exit739 740hash.exit:741 %cond.i = phi i64 [ %or11.i, %cond.true.i ], [ %or17.i, %cond.false.i ]742 %shr.29.i = lshr i64 %cond.i, 17743 %conv18.i = trunc i64 %shr.29.i to i32744 store i32 %conv18.i, ptr @lock, align 4745 %rem.i = srem i64 %cond.i, 1050011746 %conv19.i = trunc i64 %rem.i to i32747 store i32 %conv19.i, ptr @htindex, align 4748 %rem20.i = urem i32 %conv18.i, 179749 %add.i = or i32 %rem20.i, 131072750 store i32 %add.i, ptr @stride, align 4751 %8 = load ptr, ptr @ht, align 8752 %arrayidx = getelementptr inbounds i32, ptr %8, i64 %rem.i753 %9 = load i32, ptr %arrayidx, align 4754 %cmp1 = icmp eq i32 %9, %conv18.i755 br i1 %cmp1, label %if.then, label %if.end756 757if.then:758 %idxprom.lcssa = phi i64 [ %rem.i, %hash.exit ], [ %idxprom.1, %if.end ], [ %idxprom.2, %if.end.1 ], [ %idxprom.3, %if.end.2 ], [ %idxprom.4, %if.end.3 ], [ %idxprom.5, %if.end.4 ], [ %idxprom.6, %if.end.5 ], [ %idxprom.7, %if.end.6 ]759 %10 = load ptr, ptr @he, align 8760 %arrayidx3 = getelementptr inbounds i8, ptr %10, i64 %idxprom.lcssa761 %11 = load i8, ptr %arrayidx3, align 1762 %conv = sext i8 %11 to i32763 br label %cleanup764 765if.end:766 %add = add nsw i32 %add.i, %conv19.i767 %cmp4 = icmp sgt i32 %add, 1050010768 %sub = add nsw i32 %add, -1050011769 %sub.add = select i1 %cmp4, i32 %sub, i32 %add770 %idxprom.1 = sext i32 %sub.add to i64771 %arrayidx.1 = getelementptr inbounds i32, ptr %8, i64 %idxprom.1772 %12 = load i32, ptr %arrayidx.1, align 4773 %cmp1.1 = icmp eq i32 %12, %conv18.i774 br i1 %cmp1.1, label %if.then, label %if.end.1775 776cleanup:777 %retval.0 = phi i32 [ %conv, %if.then ], [ -128, %if.end.6 ]778 ret i32 %retval.0779 780if.end.1:781 %add.1 = add nsw i32 %add.i, %sub.add782 %cmp4.1 = icmp sgt i32 %add.1, 1050010783 %sub.1 = add nsw i32 %add.1, -1050011784 %sub.add.1 = select i1 %cmp4.1, i32 %sub.1, i32 %add.1785 %idxprom.2 = sext i32 %sub.add.1 to i64786 %arrayidx.2 = getelementptr inbounds i32, ptr %8, i64 %idxprom.2787 %13 = load i32, ptr %arrayidx.2, align 4788 %cmp1.2 = icmp eq i32 %13, %conv18.i789 br i1 %cmp1.2, label %if.then, label %if.end.2790 791if.end.2:792 %add.2 = add nsw i32 %add.i, %sub.add.1793 %cmp4.2 = icmp sgt i32 %add.2, 1050010794 %sub.2 = add nsw i32 %add.2, -1050011795 %sub.add.2 = select i1 %cmp4.2, i32 %sub.2, i32 %add.2796 %idxprom.3 = sext i32 %sub.add.2 to i64797 %arrayidx.3 = getelementptr inbounds i32, ptr %8, i64 %idxprom.3798 %14 = load i32, ptr %arrayidx.3, align 4799 %cmp1.3 = icmp eq i32 %14, %conv18.i800 br i1 %cmp1.3, label %if.then, label %if.end.3801 802if.end.3:803 %add.3 = add nsw i32 %add.i, %sub.add.2804 %cmp4.3 = icmp sgt i32 %add.3, 1050010805 %sub.3 = add nsw i32 %add.3, -1050011806 %sub.add.3 = select i1 %cmp4.3, i32 %sub.3, i32 %add.3807 %idxprom.4 = sext i32 %sub.add.3 to i64808 %arrayidx.4 = getelementptr inbounds i32, ptr %8, i64 %idxprom.4809 %15 = load i32, ptr %arrayidx.4, align 4810 %cmp1.4 = icmp eq i32 %15, %conv18.i811 br i1 %cmp1.4, label %if.then, label %if.end.4812 813if.end.4:814 %add.4 = add nsw i32 %add.i, %sub.add.3815 %cmp4.4 = icmp sgt i32 %add.4, 1050010816 %sub.4 = add nsw i32 %add.4, -1050011817 %sub.add.4 = select i1 %cmp4.4, i32 %sub.4, i32 %add.4818 %idxprom.5 = sext i32 %sub.add.4 to i64819 %arrayidx.5 = getelementptr inbounds i32, ptr %8, i64 %idxprom.5820 %16 = load i32, ptr %arrayidx.5, align 4821 %cmp1.5 = icmp eq i32 %16, %conv18.i822 br i1 %cmp1.5, label %if.then, label %if.end.5823 824if.end.5:825 %add.5 = add nsw i32 %add.i, %sub.add.4826 %cmp4.5 = icmp sgt i32 %add.5, 1050010827 %sub.5 = add nsw i32 %add.5, -1050011828 %sub.add.5 = select i1 %cmp4.5, i32 %sub.5, i32 %add.5829 %idxprom.6 = sext i32 %sub.add.5 to i64830 %arrayidx.6 = getelementptr inbounds i32, ptr %8, i64 %idxprom.6831 %17 = load i32, ptr %arrayidx.6, align 4832 %cmp1.6 = icmp eq i32 %17, %conv18.i833 br i1 %cmp1.6, label %if.then, label %if.end.6834 835if.end.6:836 %add.6 = add nsw i32 %add.i, %sub.add.5837 %cmp4.6 = icmp sgt i32 %add.6, 1050010838 %sub.6 = add nsw i32 %add.6, -1050011839 %sub.add.6 = select i1 %cmp4.6, i32 %sub.6, i32 %add.6840 %idxprom.7 = sext i32 %sub.add.6 to i64841 %arrayidx.7 = getelementptr inbounds i32, ptr %8, i64 %idxprom.7842 %18 = load i32, ptr %arrayidx.7, align 4843 %cmp1.7 = icmp eq i32 %18, %conv18.i844 br i1 %cmp1.7, label %if.then, label %cleanup845}846