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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9,CHECK-PWR9-LE3; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9,CHECK-PWR9-BE4; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR78,CHECK-PWR8 -implicit-check-not vabsdu5; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,CHECK-PWR78,CHECK-PWR7 -implicit-check-not vmaxsd6 7define <4 x i32> @simple_absv_32(<4 x i32> %a) local_unnamed_addr {8; CHECK-PWR9-LABEL: simple_absv_32:9; CHECK-PWR9: # %bb.0: # %entry10; CHECK-PWR9-NEXT: vnegw v3, v211; CHECK-PWR9-NEXT: vmaxsw v2, v2, v312; CHECK-PWR9-NEXT: blr13;14; CHECK-PWR78-LABEL: simple_absv_32:15; CHECK-PWR78: # %bb.0: # %entry16; CHECK-PWR78-NEXT: xxlxor v3, v3, v317; CHECK-PWR78-NEXT: vsubuwm v3, v3, v218; CHECK-PWR78-NEXT: vmaxsw v2, v2, v319; CHECK-PWR78-NEXT: blr20entry:21 %sub.i = sub <4 x i32> zeroinitializer, %a22 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i)23 ret <4 x i32> %024}25 26define <4 x i32> @simple_absv_32_swap(<4 x i32> %a) local_unnamed_addr {27; CHECK-PWR9-LABEL: simple_absv_32_swap:28; CHECK-PWR9: # %bb.0: # %entry29; CHECK-PWR9-NEXT: vnegw v3, v230; CHECK-PWR9-NEXT: vmaxsw v2, v2, v331; CHECK-PWR9-NEXT: blr32;33; CHECK-PWR78-LABEL: simple_absv_32_swap:34; CHECK-PWR78: # %bb.0: # %entry35; CHECK-PWR78-NEXT: xxlxor v3, v3, v336; CHECK-PWR78-NEXT: vsubuwm v3, v3, v237; CHECK-PWR78-NEXT: vmaxsw v2, v3, v238; CHECK-PWR78-NEXT: blr39entry:40 %sub.i = sub <4 x i32> zeroinitializer, %a41 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub.i, <4 x i32> %a)42 ret <4 x i32> %043}44 45define <8 x i16> @simple_absv_16(<8 x i16> %a) local_unnamed_addr {46; CHECK-LABEL: simple_absv_16:47; CHECK: # %bb.0: # %entry48; CHECK-NEXT: xxlxor v3, v3, v349; CHECK-NEXT: vsubuhm v3, v3, v250; CHECK-NEXT: vmaxsh v2, v2, v351; CHECK-NEXT: blr52entry:53 %sub.i = sub <8 x i16> zeroinitializer, %a54 %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %a, <8 x i16> %sub.i)55 ret <8 x i16> %056}57 58define <16 x i8> @simple_absv_8(<16 x i8> %a) local_unnamed_addr {59; CHECK-LABEL: simple_absv_8:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: xxlxor v3, v3, v362; CHECK-NEXT: vsububm v3, v3, v263; CHECK-NEXT: vmaxsb v2, v2, v364; CHECK-NEXT: blr65entry:66 %sub.i = sub <16 x i8> zeroinitializer, %a67 %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %a, <16 x i8> %sub.i)68 ret <16 x i8> %069}70 71; v2i64 vmax isn't avaiable on pwr772define <2 x i64> @sub_absv_64(<2 x i64> %a, <2 x i64> %b) local_unnamed_addr {73; CHECK-PWR9-LABEL: sub_absv_64:74; CHECK-PWR9: # %bb.0: # %entry75; CHECK-PWR9-NEXT: vsubudm v2, v2, v376; CHECK-PWR9-NEXT: vnegd v3, v277; CHECK-PWR9-NEXT: vmaxsd v2, v2, v378; CHECK-PWR9-NEXT: blr79;80; CHECK-PWR8-LABEL: sub_absv_64:81; CHECK-PWR8: # %bb.0: # %entry82; CHECK-PWR8-NEXT: vsubudm v2, v2, v383; CHECK-PWR8-NEXT: xxlxor v3, v3, v384; CHECK-PWR8-NEXT: vsubudm v3, v3, v285; CHECK-PWR8-NEXT: vmaxsd v2, v2, v386; CHECK-PWR8-NEXT: blr87;88; CHECK-PWR7-LABEL: sub_absv_64:89; CHECK-PWR7: # %bb.0: # %entry90; CHECK-PWR7-NEXT: addi r3, r1, -4891; CHECK-PWR7-NEXT: stxvd2x v2, 0, r392; CHECK-PWR7-NEXT: addi r3, r1, -3293; CHECK-PWR7-NEXT: stxvd2x v3, 0, r394; CHECK-PWR7-NEXT: ld r4, -40(r1)95; CHECK-PWR7-NEXT: ld r5, -24(r1)96; CHECK-PWR7-NEXT: ld r3, -48(r1)97; CHECK-PWR7-NEXT: sub r4, r4, r598; CHECK-PWR7-NEXT: sradi r5, r4, 6399; CHECK-PWR7-NEXT: xor r4, r4, r5100; CHECK-PWR7-NEXT: sub r4, r4, r5101; CHECK-PWR7-NEXT: ld r5, -32(r1)102; CHECK-PWR7-NEXT: std r4, -8(r1)103; CHECK-PWR7-NEXT: sub r3, r3, r5104; CHECK-PWR7-NEXT: sradi r4, r3, 63105; CHECK-PWR7-NEXT: xor r3, r3, r4106; CHECK-PWR7-NEXT: sub r3, r3, r4107; CHECK-PWR7-NEXT: std r3, -16(r1)108; CHECK-PWR7-NEXT: addi r3, r1, -16109; CHECK-PWR7-NEXT: lxvd2x v2, 0, r3110; CHECK-PWR7-NEXT: blr111entry:112 %0 = sub nsw <2 x i64> %a, %b113 %1 = icmp sgt <2 x i64> %0, <i64 -1, i64 -1>114 %2 = sub <2 x i64> zeroinitializer, %0115 %3 = select <2 x i1> %1, <2 x i64> %0, <2 x i64> %2116 ret <2 x i64> %3117}118 119; The select pattern can only be detected for v4i32.120define <4 x i32> @sub_absv_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {121; CHECK-PWR9-LABEL: sub_absv_32:122; CHECK-PWR9: # %bb.0: # %entry123; CHECK-PWR9-NEXT: xvnegsp v3, v3124; CHECK-PWR9-NEXT: xvnegsp v2, v2125; CHECK-PWR9-NEXT: vabsduw v2, v2, v3126; CHECK-PWR9-NEXT: blr127;128; CHECK-PWR78-LABEL: sub_absv_32:129; CHECK-PWR78: # %bb.0: # %entry130; CHECK-PWR78-NEXT: vsubuwm v2, v2, v3131; CHECK-PWR78-NEXT: xxlxor v3, v3, v3132; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2133; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3134; CHECK-PWR78-NEXT: blr135entry:136 %0 = sub nsw <4 x i32> %a, %b137 %1 = icmp sgt <4 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1>138 %2 = sub <4 x i32> zeroinitializer, %0139 %3 = select <4 x i1> %1, <4 x i32> %0, <4 x i32> %2140 ret <4 x i32> %3141}142 143define <8 x i16> @sub_absv_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {144; CHECK-LABEL: sub_absv_16:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsubuhm v2, v2, v3147; CHECK-NEXT: xxlxor v3, v3, v3148; CHECK-NEXT: vsubuhm v3, v3, v2149; CHECK-NEXT: vmaxsh v2, v2, v3150; CHECK-NEXT: blr151entry:152 %0 = sub nsw <8 x i16> %a, %b153 %1 = icmp sgt <8 x i16> %0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>154 %2 = sub <8 x i16> zeroinitializer, %0155 %3 = select <8 x i1> %1, <8 x i16> %0, <8 x i16> %2156 ret <8 x i16> %3157}158 159define <16 x i8> @sub_absv_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {160; CHECK-LABEL: sub_absv_8:161; CHECK: # %bb.0: # %entry162; CHECK-NEXT: vsububm v2, v2, v3163; CHECK-NEXT: xxlxor v3, v3, v3164; CHECK-NEXT: vsububm v3, v3, v2165; CHECK-NEXT: vmaxsb v2, v2, v3166; CHECK-NEXT: blr167entry:168 %0 = sub nsw <16 x i8> %a, %b169 %1 = icmp sgt <16 x i8> %0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>170 %2 = sub <16 x i8> zeroinitializer, %0171 %3 = select <16 x i1> %1, <16 x i8> %0, <16 x i8> %2172 ret <16 x i8> %3173}174 175define <8 x i16> @sub_absv_16_ext(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {176; CHECK-LABEL: sub_absv_16_ext:177; CHECK: # %bb.0: # %entry178; CHECK-NEXT: vminsh v4, v2, v3179; CHECK-NEXT: vmaxsh v2, v2, v3180; CHECK-NEXT: vsubuhm v2, v2, v4181; CHECK-NEXT: blr182entry:183 %0 = sext <8 x i16> %a to <8 x i32>184 %1 = sext <8 x i16> %b to <8 x i32>185 %2 = sub nsw <8 x i32> %0, %1186 %3 = icmp sgt <8 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>187 %4 = sub nsw <8 x i32> zeroinitializer, %2188 %5 = select <8 x i1> %3, <8 x i32> %2, <8 x i32> %4189 %6 = trunc <8 x i32> %5 to <8 x i16>190 ret <8 x i16> %6191}192 193define <16 x i8> @sub_absv_8_ext(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {194; CHECK-PWR9-LABEL: sub_absv_8_ext:195; CHECK-PWR9: # %bb.0: # %entry196; CHECK-PWR9-NEXT: vabsdub v2, v2, v3197; CHECK-PWR9-NEXT: blr198;199; CHECK-PWR78-LABEL: sub_absv_8_ext:200; CHECK-PWR78: # %bb.0: # %entry201; CHECK-PWR78-NEXT: vminub v4, v2, v3202; CHECK-PWR78-NEXT: vmaxub v2, v2, v3203; CHECK-PWR78-NEXT: vsububm v2, v2, v4204; CHECK-PWR78-NEXT: blr205entry:206 %0 = zext <16 x i8> %a to <16 x i32>207 %1 = zext <16 x i8> %b to <16 x i32>208 %2 = sub nsw <16 x i32> %0, %1209 %3 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %2, i1 true)210 %4 = trunc <16 x i32> %3 to <16 x i8>211 ret <16 x i8> %4212}213 214define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {215; CHECK-PWR9-LABEL: sub_absv_vec_32:216; CHECK-PWR9: # %bb.0: # %entry217; CHECK-PWR9-NEXT: xvnegsp v3, v3218; CHECK-PWR9-NEXT: xvnegsp v2, v2219; CHECK-PWR9-NEXT: vabsduw v2, v2, v3220; CHECK-PWR9-NEXT: blr221;222; CHECK-PWR78-LABEL: sub_absv_vec_32:223; CHECK-PWR78: # %bb.0: # %entry224; CHECK-PWR78-NEXT: vsubuwm v2, v2, v3225; CHECK-PWR78-NEXT: xxlxor v3, v3, v3226; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2227; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3228; CHECK-PWR78-NEXT: blr229entry:230 %sub = sub nsw <4 x i32> %a, %b231 %sub.i = sub <4 x i32> zeroinitializer, %sub232 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub, <4 x i32> %sub.i)233 ret <4 x i32> %0234}235 236define <8 x i16> @sub_absv_vec_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {237; CHECK-LABEL: sub_absv_vec_16:238; CHECK: # %bb.0: # %entry239; CHECK-NEXT: vsubuhm v2, v2, v3240; CHECK-NEXT: xxlxor v3, v3, v3241; CHECK-NEXT: vsubuhm v3, v3, v2242; CHECK-NEXT: vmaxsh v2, v2, v3243; CHECK-NEXT: blr244entry:245 %sub = sub nsw <8 x i16> %a, %b246 %sub.i = sub <8 x i16> zeroinitializer, %sub247 %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %sub, <8 x i16> %sub.i)248 ret <8 x i16> %0249}250 251define <16 x i8> @sub_absv_vec_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {252; CHECK-LABEL: sub_absv_vec_8:253; CHECK: # %bb.0: # %entry254; CHECK-NEXT: vsububm v2, v2, v3255; CHECK-NEXT: xxlxor v3, v3, v3256; CHECK-NEXT: vsububm v3, v3, v2257; CHECK-NEXT: vmaxsb v2, v2, v3258; CHECK-NEXT: blr259entry:260 %sub = sub nsw <16 x i8> %a, %b261 %sub.i = sub <16 x i8> zeroinitializer, %sub262 %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %sub, <16 x i8> %sub.i)263 ret <16 x i8> %0264}265 266define <4 x i32> @zext_sub_absd32(<4 x i16>, <4 x i16>) local_unnamed_addr {267; CHECK-PWR9-LE-LABEL: zext_sub_absd32:268; CHECK-PWR9-LE: # %bb.0:269; CHECK-PWR9-LE-NEXT: vabsduh v2, v2, v3270; CHECK-PWR9-LE-NEXT: xxlxor v3, v3, v3271; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2272; CHECK-PWR9-LE-NEXT: blr273;274; CHECK-PWR9-BE-LABEL: zext_sub_absd32:275; CHECK-PWR9-BE: # %bb.0:276; CHECK-PWR9-BE-NEXT: vabsduh v2, v2, v3277; CHECK-PWR9-BE-NEXT: xxlxor v3, v3, v3278; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2279; CHECK-PWR9-BE-NEXT: blr280;281; CHECK-PWR8-LABEL: zext_sub_absd32:282; CHECK-PWR8: # %bb.0:283; CHECK-PWR8-NEXT: xxlxor v4, v4, v4284; CHECK-PWR8-NEXT: vmrglh v2, v4, v2285; CHECK-PWR8-NEXT: vmrglh v3, v4, v3286; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3287; CHECK-PWR8-NEXT: vsubuwm v3, v4, v2288; CHECK-PWR8-NEXT: vmaxsw v2, v2, v3289; CHECK-PWR8-NEXT: blr290;291; CHECK-PWR7-LABEL: zext_sub_absd32:292; CHECK-PWR7: # %bb.0:293; CHECK-PWR7-NEXT: addis r3, r2, .LCPI13_0@toc@ha294; CHECK-PWR7-NEXT: xxlxor v5, v5, v5295; CHECK-PWR7-NEXT: addi r3, r3, .LCPI13_0@toc@l296; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3297; CHECK-PWR7-NEXT: vperm v2, v5, v2, v4298; CHECK-PWR7-NEXT: vperm v3, v5, v3, v4299; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3300; CHECK-PWR7-NEXT: vsubuwm v3, v5, v2301; CHECK-PWR7-NEXT: vmaxsw v2, v2, v3302; CHECK-PWR7-NEXT: blr303 %3 = zext <4 x i16> %0 to <4 x i32>304 %4 = zext <4 x i16> %1 to <4 x i32>305 %5 = sub <4 x i32> %3, %4306 %6 = sub <4 x i32> zeroinitializer, %5307 %7 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> %6)308 ret <4 x i32> %7309}310 311define <8 x i16> @zext_sub_absd16(<8 x i8>, <8 x i8>) local_unnamed_addr {312; CHECK-PWR9-LE-LABEL: zext_sub_absd16:313; CHECK-PWR9-LE: # %bb.0:314; CHECK-PWR9-LE-NEXT: vabsdub v2, v2, v3315; CHECK-PWR9-LE-NEXT: xxlxor v3, v3, v3316; CHECK-PWR9-LE-NEXT: vmrglb v2, v3, v2317; CHECK-PWR9-LE-NEXT: blr318;319; CHECK-PWR9-BE-LABEL: zext_sub_absd16:320; CHECK-PWR9-BE: # %bb.0:321; CHECK-PWR9-BE-NEXT: vabsdub v2, v2, v3322; CHECK-PWR9-BE-NEXT: xxlxor v3, v3, v3323; CHECK-PWR9-BE-NEXT: vmrghb v2, v3, v2324; CHECK-PWR9-BE-NEXT: blr325;326; CHECK-PWR8-LABEL: zext_sub_absd16:327; CHECK-PWR8: # %bb.0:328; CHECK-PWR8-NEXT: xxlxor v4, v4, v4329; CHECK-PWR8-NEXT: vmrglb v2, v4, v2330; CHECK-PWR8-NEXT: vmrglb v3, v4, v3331; CHECK-PWR8-NEXT: vsubuhm v2, v2, v3332; CHECK-PWR8-NEXT: vsubuhm v3, v4, v2333; CHECK-PWR8-NEXT: vmaxsh v2, v2, v3334; CHECK-PWR8-NEXT: blr335;336; CHECK-PWR7-LABEL: zext_sub_absd16:337; CHECK-PWR7: # %bb.0:338; CHECK-PWR7-NEXT: addis r3, r2, .LCPI14_0@toc@ha339; CHECK-PWR7-NEXT: xxlxor v5, v5, v5340; CHECK-PWR7-NEXT: addi r3, r3, .LCPI14_0@toc@l341; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3342; CHECK-PWR7-NEXT: vperm v2, v5, v2, v4343; CHECK-PWR7-NEXT: vperm v3, v5, v3, v4344; CHECK-PWR7-NEXT: vsubuhm v2, v2, v3345; CHECK-PWR7-NEXT: vsubuhm v3, v5, v2346; CHECK-PWR7-NEXT: vmaxsh v2, v2, v3347; CHECK-PWR7-NEXT: blr348 %3 = zext <8 x i8> %0 to <8 x i16>349 %4 = zext <8 x i8> %1 to <8 x i16>350 %5 = sub <8 x i16> %3, %4351 %6 = sub <8 x i16> zeroinitializer, %5352 %7 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> %6)353 ret <8 x i16> %7354}355 356define <16 x i8> @zext_sub_absd8(<16 x i4>, <16 x i4>) local_unnamed_addr {357; CHECK-PWR9-LABEL: zext_sub_absd8:358; CHECK-PWR9: # %bb.0:359; CHECK-PWR9-NEXT: xxspltib vs0, 15360; CHECK-PWR9-NEXT: xxland v3, v3, vs0361; CHECK-PWR9-NEXT: xxland v2, v2, vs0362; CHECK-PWR9-NEXT: vabsdub v2, v2, v3363; CHECK-PWR9-NEXT: blr364;365; CHECK-PWR78-LABEL: zext_sub_absd8:366; CHECK-PWR78: # %bb.0:367; CHECK-PWR78-NEXT: vspltisb v4, 15368; CHECK-PWR78-NEXT: xxland v2, v2, v4369; CHECK-PWR78-NEXT: xxland v3, v3, v4370; CHECK-PWR78-NEXT: vsububm v2, v2, v3371; CHECK-PWR78-NEXT: xxlxor v3, v3, v3372; CHECK-PWR78-NEXT: vsububm v3, v3, v2373; CHECK-PWR78-NEXT: vmaxsb v2, v2, v3374; CHECK-PWR78-NEXT: blr375 %3 = zext <16 x i4> %0 to <16 x i8>376 %4 = zext <16 x i4> %1 to <16 x i8>377 %5 = sub <16 x i8> %3, %4378 %6 = sub <16 x i8> zeroinitializer, %5379 %7 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %5, <16 x i8> %6)380 ret <16 x i8> %7381}382 383define <4 x i32> @sext_sub_absd32(<4 x i16>, <4 x i16>) local_unnamed_addr {384; CHECK-PWR9-LE-LABEL: sext_sub_absd32:385; CHECK-PWR9-LE: # %bb.0:386; CHECK-PWR9-LE-NEXT: vminsh v4, v2, v3387; CHECK-PWR9-LE-NEXT: vmaxsh v2, v2, v3388; CHECK-PWR9-LE-NEXT: xxlxor v3, v3, v3389; CHECK-PWR9-LE-NEXT: vsubuhm v2, v2, v4390; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2391; CHECK-PWR9-LE-NEXT: blr392;393; CHECK-PWR9-BE-LABEL: sext_sub_absd32:394; CHECK-PWR9-BE: # %bb.0:395; CHECK-PWR9-BE-NEXT: vminsh v4, v2, v3396; CHECK-PWR9-BE-NEXT: vmaxsh v2, v2, v3397; CHECK-PWR9-BE-NEXT: xxlxor v3, v3, v3398; CHECK-PWR9-BE-NEXT: vsubuhm v2, v2, v4399; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2400; CHECK-PWR9-BE-NEXT: blr401;402; CHECK-PWR8-LABEL: sext_sub_absd32:403; CHECK-PWR8: # %bb.0:404; CHECK-PWR8-NEXT: vspltisw v4, 8405; CHECK-PWR8-NEXT: vmrglh v2, v2, v2406; CHECK-PWR8-NEXT: vadduwm v4, v4, v4407; CHECK-PWR8-NEXT: vmrglh v3, v3, v3408; CHECK-PWR8-NEXT: vslw v2, v2, v4409; CHECK-PWR8-NEXT: vslw v3, v3, v4410; CHECK-PWR8-NEXT: vsraw v2, v2, v4411; CHECK-PWR8-NEXT: vsraw v3, v3, v4412; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3413; CHECK-PWR8-NEXT: xxlxor v3, v3, v3414; CHECK-PWR8-NEXT: vsubuwm v3, v3, v2415; CHECK-PWR8-NEXT: vmaxsw v2, v2, v3416; CHECK-PWR8-NEXT: blr417;418; CHECK-PWR7-LABEL: sext_sub_absd32:419; CHECK-PWR7: # %bb.0:420; CHECK-PWR7-NEXT: vspltisw v4, 8421; CHECK-PWR7-NEXT: vmrghh v2, v2, v2422; CHECK-PWR7-NEXT: vmrghh v3, v3, v3423; CHECK-PWR7-NEXT: vadduwm v4, v4, v4424; CHECK-PWR7-NEXT: vslw v2, v2, v4425; CHECK-PWR7-NEXT: vslw v3, v3, v4426; CHECK-PWR7-NEXT: vsraw v2, v2, v4427; CHECK-PWR7-NEXT: vsraw v3, v3, v4428; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3429; CHECK-PWR7-NEXT: xxlxor v3, v3, v3430; CHECK-PWR7-NEXT: vsubuwm v3, v3, v2431; CHECK-PWR7-NEXT: vmaxsw v2, v2, v3432; CHECK-PWR7-NEXT: blr433 %3 = sext <4 x i16> %0 to <4 x i32>434 %4 = sext <4 x i16> %1 to <4 x i32>435 %5 = sub <4 x i32> %3, %4436 %6 = sub <4 x i32> zeroinitializer, %5437 %7 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> %6)438 ret <4 x i32> %7439}440 441define <8 x i16> @sext_sub_absd16(<8 x i8>, <8 x i8>) local_unnamed_addr {442; CHECK-PWR9-LE-LABEL: sext_sub_absd16:443; CHECK-PWR9-LE: # %bb.0:444; CHECK-PWR9-LE-NEXT: vminsb v4, v2, v3445; CHECK-PWR9-LE-NEXT: vmaxsb v2, v2, v3446; CHECK-PWR9-LE-NEXT: xxlxor v3, v3, v3447; CHECK-PWR9-LE-NEXT: vsububm v2, v2, v4448; CHECK-PWR9-LE-NEXT: vmrglb v2, v3, v2449; CHECK-PWR9-LE-NEXT: blr450;451; CHECK-PWR9-BE-LABEL: sext_sub_absd16:452; CHECK-PWR9-BE: # %bb.0:453; CHECK-PWR9-BE-NEXT: vminsb v4, v2, v3454; CHECK-PWR9-BE-NEXT: vmaxsb v2, v2, v3455; CHECK-PWR9-BE-NEXT: xxlxor v3, v3, v3456; CHECK-PWR9-BE-NEXT: vsububm v2, v2, v4457; CHECK-PWR9-BE-NEXT: vmrghb v2, v3, v2458; CHECK-PWR9-BE-NEXT: blr459;460; CHECK-PWR8-LABEL: sext_sub_absd16:461; CHECK-PWR8: # %bb.0:462; CHECK-PWR8-NEXT: vmrglb v2, v2, v2463; CHECK-PWR8-NEXT: vspltish v4, 8464; CHECK-PWR8-NEXT: vslh v2, v2, v4465; CHECK-PWR8-NEXT: vmrglb v3, v3, v3466; CHECK-PWR8-NEXT: vslh v3, v3, v4467; CHECK-PWR8-NEXT: vsrah v2, v2, v4468; CHECK-PWR8-NEXT: vsrah v3, v3, v4469; CHECK-PWR8-NEXT: vsubuhm v2, v2, v3470; CHECK-PWR8-NEXT: xxlxor v3, v3, v3471; CHECK-PWR8-NEXT: vsubuhm v3, v3, v2472; CHECK-PWR8-NEXT: vmaxsh v2, v2, v3473; CHECK-PWR8-NEXT: blr474;475; CHECK-PWR7-LABEL: sext_sub_absd16:476; CHECK-PWR7: # %bb.0:477; CHECK-PWR7-NEXT: vspltish v4, 8478; CHECK-PWR7-NEXT: vmrghb v2, v2, v2479; CHECK-PWR7-NEXT: vmrghb v3, v3, v3480; CHECK-PWR7-NEXT: vslh v2, v2, v4481; CHECK-PWR7-NEXT: vslh v3, v3, v4482; CHECK-PWR7-NEXT: vsrah v2, v2, v4483; CHECK-PWR7-NEXT: vsrah v3, v3, v4484; CHECK-PWR7-NEXT: vsubuhm v2, v2, v3485; CHECK-PWR7-NEXT: xxlxor v3, v3, v3486; CHECK-PWR7-NEXT: vsubuhm v3, v3, v2487; CHECK-PWR7-NEXT: vmaxsh v2, v2, v3488; CHECK-PWR7-NEXT: blr489 %3 = sext <8 x i8> %0 to <8 x i16>490 %4 = sext <8 x i8> %1 to <8 x i16>491 %5 = sub <8 x i16> %3, %4492 %6 = sub <8 x i16> zeroinitializer, %5493 %7 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> %6)494 ret <8 x i16> %7495}496 497define <16 x i8> @sext_sub_absd8(<16 x i4>, <16 x i4>) local_unnamed_addr {498; CHECK-PWR9-LABEL: sext_sub_absd8:499; CHECK-PWR9: # %bb.0:500; CHECK-PWR9-NEXT: xxspltib v4, 4501; CHECK-PWR9-NEXT: vslb v3, v3, v4502; CHECK-PWR9-NEXT: vslb v2, v2, v4503; CHECK-PWR9-NEXT: vsrab v3, v3, v4504; CHECK-PWR9-NEXT: vsrab v2, v2, v4505; CHECK-PWR9-NEXT: vminsb v4, v2, v3506; CHECK-PWR9-NEXT: vmaxsb v2, v2, v3507; CHECK-PWR9-NEXT: vsububm v2, v2, v4508; CHECK-PWR9-NEXT: blr509;510; CHECK-PWR78-LABEL: sext_sub_absd8:511; CHECK-PWR78: # %bb.0:512; CHECK-PWR78-NEXT: vspltisb v4, 4513; CHECK-PWR78-NEXT: vslb v2, v2, v4514; CHECK-PWR78-NEXT: vslb v3, v3, v4515; CHECK-PWR78-NEXT: vsrab v2, v2, v4516; CHECK-PWR78-NEXT: vsrab v3, v3, v4517; CHECK-PWR78-NEXT: vsububm v2, v2, v3518; CHECK-PWR78-NEXT: xxlxor v3, v3, v3519; CHECK-PWR78-NEXT: vsububm v3, v3, v2520; CHECK-PWR78-NEXT: vmaxsb v2, v2, v3521; CHECK-PWR78-NEXT: blr522 %3 = sext <16 x i4> %0 to <16 x i8>523 %4 = sext <16 x i4> %1 to <16 x i8>524 %5 = sub <16 x i8> %3, %4525 %6 = sub <16 x i8> zeroinitializer, %5526 %7 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %5, <16 x i8> %6)527 ret <16 x i8> %7528}529 530; To verify vabsdu* exploitation for ucmp + sub + select sequence531 532define <4 x i32> @absd_int32_ugt(<4 x i32>, <4 x i32>) {533; CHECK-PWR9-LABEL: absd_int32_ugt:534; CHECK-PWR9: # %bb.0:535; CHECK-PWR9-NEXT: vabsduw v2, v2, v3536; CHECK-PWR9-NEXT: blr537;538; CHECK-PWR78-LABEL: absd_int32_ugt:539; CHECK-PWR78: # %bb.0:540; CHECK-PWR78-NEXT: vminuw v4, v2, v3541; CHECK-PWR78-NEXT: vmaxuw v2, v2, v3542; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4543; CHECK-PWR78-NEXT: blr544 %3 = icmp ugt <4 x i32> %0, %1545 %4 = sub <4 x i32> %0, %1546 %5 = sub <4 x i32> %1, %0547 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5548 ret <4 x i32> %6549}550 551define <4 x i32> @absd_int32_uge(<4 x i32>, <4 x i32>) {552; CHECK-PWR9-LABEL: absd_int32_uge:553; CHECK-PWR9: # %bb.0:554; CHECK-PWR9-NEXT: vabsduw v2, v2, v3555; CHECK-PWR9-NEXT: blr556;557; CHECK-PWR78-LABEL: absd_int32_uge:558; CHECK-PWR78: # %bb.0:559; CHECK-PWR78-NEXT: vminuw v4, v2, v3560; CHECK-PWR78-NEXT: vmaxuw v2, v2, v3561; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4562; CHECK-PWR78-NEXT: blr563 %3 = icmp uge <4 x i32> %0, %1564 %4 = sub <4 x i32> %0, %1565 %5 = sub <4 x i32> %1, %0566 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5567 ret <4 x i32> %6568}569 570define <4 x i32> @absd_int32_ult(<4 x i32>, <4 x i32>) {571; CHECK-PWR9-LABEL: absd_int32_ult:572; CHECK-PWR9: # %bb.0:573; CHECK-PWR9-NEXT: vabsduw v2, v2, v3574; CHECK-PWR9-NEXT: blr575;576; CHECK-PWR78-LABEL: absd_int32_ult:577; CHECK-PWR78: # %bb.0:578; CHECK-PWR78-NEXT: vminuw v4, v2, v3579; CHECK-PWR78-NEXT: vmaxuw v2, v2, v3580; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4581; CHECK-PWR78-NEXT: blr582 %3 = icmp ult <4 x i32> %0, %1583 %4 = sub <4 x i32> %0, %1584 %5 = sub <4 x i32> %1, %0585 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4586 ret <4 x i32> %6587}588 589define <4 x i32> @absd_int32_ule(<4 x i32>, <4 x i32>) {590; CHECK-PWR9-LABEL: absd_int32_ule:591; CHECK-PWR9: # %bb.0:592; CHECK-PWR9-NEXT: vabsduw v2, v2, v3593; CHECK-PWR9-NEXT: blr594;595; CHECK-PWR78-LABEL: absd_int32_ule:596; CHECK-PWR78: # %bb.0:597; CHECK-PWR78-NEXT: vminuw v4, v2, v3598; CHECK-PWR78-NEXT: vmaxuw v2, v2, v3599; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4600; CHECK-PWR78-NEXT: blr601 %3 = icmp ule <4 x i32> %0, %1602 %4 = sub <4 x i32> %0, %1603 %5 = sub <4 x i32> %1, %0604 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4605 ret <4 x i32> %6606}607 608define <8 x i16> @absd_int16_ugt(<8 x i16>, <8 x i16>) {609; CHECK-PWR9-LABEL: absd_int16_ugt:610; CHECK-PWR9: # %bb.0:611; CHECK-PWR9-NEXT: vabsduh v2, v2, v3612; CHECK-PWR9-NEXT: blr613;614; CHECK-PWR78-LABEL: absd_int16_ugt:615; CHECK-PWR78: # %bb.0:616; CHECK-PWR78-NEXT: vminuh v4, v2, v3617; CHECK-PWR78-NEXT: vmaxuh v2, v2, v3618; CHECK-PWR78-NEXT: vsubuhm v2, v2, v4619; CHECK-PWR78-NEXT: blr620 %3 = icmp ugt <8 x i16> %0, %1621 %4 = sub <8 x i16> %0, %1622 %5 = sub <8 x i16> %1, %0623 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5624 ret <8 x i16> %6625}626 627define <8 x i16> @absd_int16_uge(<8 x i16>, <8 x i16>) {628; CHECK-PWR9-LABEL: absd_int16_uge:629; CHECK-PWR9: # %bb.0:630; CHECK-PWR9-NEXT: vabsduh v2, v2, v3631; CHECK-PWR9-NEXT: blr632;633; CHECK-PWR78-LABEL: absd_int16_uge:634; CHECK-PWR78: # %bb.0:635; CHECK-PWR78-NEXT: vminuh v4, v2, v3636; CHECK-PWR78-NEXT: vmaxuh v2, v2, v3637; CHECK-PWR78-NEXT: vsubuhm v2, v2, v4638; CHECK-PWR78-NEXT: blr639 %3 = icmp uge <8 x i16> %0, %1640 %4 = sub <8 x i16> %0, %1641 %5 = sub <8 x i16> %1, %0642 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5643 ret <8 x i16> %6644}645 646define <8 x i16> @absd_int16_ult(<8 x i16>, <8 x i16>) {647; CHECK-PWR9-LABEL: absd_int16_ult:648; CHECK-PWR9: # %bb.0:649; CHECK-PWR9-NEXT: vabsduh v2, v2, v3650; CHECK-PWR9-NEXT: blr651;652; CHECK-PWR78-LABEL: absd_int16_ult:653; CHECK-PWR78: # %bb.0:654; CHECK-PWR78-NEXT: vminuh v4, v2, v3655; CHECK-PWR78-NEXT: vmaxuh v2, v2, v3656; CHECK-PWR78-NEXT: vsubuhm v2, v2, v4657; CHECK-PWR78-NEXT: blr658 %3 = icmp ult <8 x i16> %0, %1659 %4 = sub <8 x i16> %0, %1660 %5 = sub <8 x i16> %1, %0661 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4662 ret <8 x i16> %6663}664 665define <8 x i16> @absd_int16_ule(<8 x i16>, <8 x i16>) {666; CHECK-PWR9-LABEL: absd_int16_ule:667; CHECK-PWR9: # %bb.0:668; CHECK-PWR9-NEXT: vabsduh v2, v2, v3669; CHECK-PWR9-NEXT: blr670;671; CHECK-PWR78-LABEL: absd_int16_ule:672; CHECK-PWR78: # %bb.0:673; CHECK-PWR78-NEXT: vminuh v4, v2, v3674; CHECK-PWR78-NEXT: vmaxuh v2, v2, v3675; CHECK-PWR78-NEXT: vsubuhm v2, v2, v4676; CHECK-PWR78-NEXT: blr677 %3 = icmp ule <8 x i16> %0, %1678 %4 = sub <8 x i16> %0, %1679 %5 = sub <8 x i16> %1, %0680 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4681 ret <8 x i16> %6682}683 684define <16 x i8> @absd_int8_ugt(<16 x i8>, <16 x i8>) {685; CHECK-PWR9-LABEL: absd_int8_ugt:686; CHECK-PWR9: # %bb.0:687; CHECK-PWR9-NEXT: vabsdub v2, v2, v3688; CHECK-PWR9-NEXT: blr689;690; CHECK-PWR78-LABEL: absd_int8_ugt:691; CHECK-PWR78: # %bb.0:692; CHECK-PWR78-NEXT: vminub v4, v2, v3693; CHECK-PWR78-NEXT: vmaxub v2, v2, v3694; CHECK-PWR78-NEXT: vsububm v2, v2, v4695; CHECK-PWR78-NEXT: blr696 %3 = icmp ugt <16 x i8> %0, %1697 %4 = sub <16 x i8> %0, %1698 %5 = sub <16 x i8> %1, %0699 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5700 ret <16 x i8> %6701}702 703define <16 x i8> @absd_int8_uge(<16 x i8>, <16 x i8>) {704; CHECK-PWR9-LABEL: absd_int8_uge:705; CHECK-PWR9: # %bb.0:706; CHECK-PWR9-NEXT: vabsdub v2, v2, v3707; CHECK-PWR9-NEXT: blr708;709; CHECK-PWR78-LABEL: absd_int8_uge:710; CHECK-PWR78: # %bb.0:711; CHECK-PWR78-NEXT: vminub v4, v2, v3712; CHECK-PWR78-NEXT: vmaxub v2, v2, v3713; CHECK-PWR78-NEXT: vsububm v2, v2, v4714; CHECK-PWR78-NEXT: blr715 %3 = icmp uge <16 x i8> %0, %1716 %4 = sub <16 x i8> %0, %1717 %5 = sub <16 x i8> %1, %0718 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5719 ret <16 x i8> %6720}721 722define <16 x i8> @absd_int8_ult(<16 x i8>, <16 x i8>) {723; CHECK-PWR9-LABEL: absd_int8_ult:724; CHECK-PWR9: # %bb.0:725; CHECK-PWR9-NEXT: vabsdub v2, v2, v3726; CHECK-PWR9-NEXT: blr727;728; CHECK-PWR78-LABEL: absd_int8_ult:729; CHECK-PWR78: # %bb.0:730; CHECK-PWR78-NEXT: vminub v4, v2, v3731; CHECK-PWR78-NEXT: vmaxub v2, v2, v3732; CHECK-PWR78-NEXT: vsububm v2, v2, v4733; CHECK-PWR78-NEXT: blr734 %3 = icmp ult <16 x i8> %0, %1735 %4 = sub <16 x i8> %0, %1736 %5 = sub <16 x i8> %1, %0737 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4738 ret <16 x i8> %6739}740 741define <16 x i8> @absd_int8_ule(<16 x i8>, <16 x i8>) {742; CHECK-PWR9-LABEL: absd_int8_ule:743; CHECK-PWR9: # %bb.0:744; CHECK-PWR9-NEXT: vabsdub v2, v2, v3745; CHECK-PWR9-NEXT: blr746;747; CHECK-PWR78-LABEL: absd_int8_ule:748; CHECK-PWR78: # %bb.0:749; CHECK-PWR78-NEXT: vminub v4, v2, v3750; CHECK-PWR78-NEXT: vmaxub v2, v2, v3751; CHECK-PWR78-NEXT: vsububm v2, v2, v4752; CHECK-PWR78-NEXT: blr753 %3 = icmp ule <16 x i8> %0, %1754 %4 = sub <16 x i8> %0, %1755 %5 = sub <16 x i8> %1, %0756 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4757 ret <16 x i8> %6758}759 760; Tests for ABDS icmp + sub + select sequence761 762define <4 x i32> @absd_int32_sgt(<4 x i32>, <4 x i32>) {763; CHECK-PWR9-LABEL: absd_int32_sgt:764; CHECK-PWR9: # %bb.0:765; CHECK-PWR9-NEXT: xvnegsp v3, v3766; CHECK-PWR9-NEXT: xvnegsp v2, v2767; CHECK-PWR9-NEXT: vabsduw v2, v2, v3768; CHECK-PWR9-NEXT: blr769;770; CHECK-PWR78-LABEL: absd_int32_sgt:771; CHECK-PWR78: # %bb.0:772; CHECK-PWR78-NEXT: vminsw v4, v2, v3773; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3774; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4775; CHECK-PWR78-NEXT: blr776 %3 = icmp sgt <4 x i32> %0, %1777 %4 = sub <4 x i32> %0, %1778 %5 = sub <4 x i32> %1, %0779 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5780 ret <4 x i32> %6781}782 783define <4 x i32> @absd_int32_sge(<4 x i32>, <4 x i32>) {784; CHECK-PWR9-LABEL: absd_int32_sge:785; CHECK-PWR9: # %bb.0:786; CHECK-PWR9-NEXT: xvnegsp v3, v3787; CHECK-PWR9-NEXT: xvnegsp v2, v2788; CHECK-PWR9-NEXT: vabsduw v2, v2, v3789; CHECK-PWR9-NEXT: blr790;791; CHECK-PWR78-LABEL: absd_int32_sge:792; CHECK-PWR78: # %bb.0:793; CHECK-PWR78-NEXT: vminsw v4, v2, v3794; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3795; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4796; CHECK-PWR78-NEXT: blr797 %3 = icmp sge <4 x i32> %0, %1798 %4 = sub <4 x i32> %0, %1799 %5 = sub <4 x i32> %1, %0800 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5801 ret <4 x i32> %6802}803 804define <4 x i32> @absd_int32_slt(<4 x i32>, <4 x i32>) {805; CHECK-PWR9-LABEL: absd_int32_slt:806; CHECK-PWR9: # %bb.0:807; CHECK-PWR9-NEXT: xvnegsp v3, v3808; CHECK-PWR9-NEXT: xvnegsp v2, v2809; CHECK-PWR9-NEXT: vabsduw v2, v2, v3810; CHECK-PWR9-NEXT: blr811;812; CHECK-PWR78-LABEL: absd_int32_slt:813; CHECK-PWR78: # %bb.0:814; CHECK-PWR78-NEXT: vminsw v4, v2, v3815; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3816; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4817; CHECK-PWR78-NEXT: blr818 %3 = icmp slt <4 x i32> %0, %1819 %4 = sub <4 x i32> %0, %1820 %5 = sub <4 x i32> %1, %0821 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4822 ret <4 x i32> %6823}824 825define <4 x i32> @absd_int32_sle(<4 x i32>, <4 x i32>) {826; CHECK-PWR9-LABEL: absd_int32_sle:827; CHECK-PWR9: # %bb.0:828; CHECK-PWR9-NEXT: xvnegsp v3, v3829; CHECK-PWR9-NEXT: xvnegsp v2, v2830; CHECK-PWR9-NEXT: vabsduw v2, v2, v3831; CHECK-PWR9-NEXT: blr832;833; CHECK-PWR78-LABEL: absd_int32_sle:834; CHECK-PWR78: # %bb.0:835; CHECK-PWR78-NEXT: vminsw v4, v2, v3836; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3837; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4838; CHECK-PWR78-NEXT: blr839 %3 = icmp sle <4 x i32> %0, %1840 %4 = sub <4 x i32> %0, %1841 %5 = sub <4 x i32> %1, %0842 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4843 ret <4 x i32> %6844}845 846define <8 x i16> @absd_int16_sgt(<8 x i16>, <8 x i16>) {847; CHECK-LABEL: absd_int16_sgt:848; CHECK: # %bb.0:849; CHECK-NEXT: vminsh v4, v2, v3850; CHECK-NEXT: vmaxsh v2, v2, v3851; CHECK-NEXT: vsubuhm v2, v2, v4852; CHECK-NEXT: blr853 %3 = icmp sgt <8 x i16> %0, %1854 %4 = sub <8 x i16> %0, %1855 %5 = sub <8 x i16> %1, %0856 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5857 ret <8 x i16> %6858}859 860define <8 x i16> @absd_int16_sge(<8 x i16>, <8 x i16>) {861; CHECK-LABEL: absd_int16_sge:862; CHECK: # %bb.0:863; CHECK-NEXT: vminsh v4, v2, v3864; CHECK-NEXT: vmaxsh v2, v2, v3865; CHECK-NEXT: vsubuhm v2, v2, v4866; CHECK-NEXT: blr867 %3 = icmp sge <8 x i16> %0, %1868 %4 = sub <8 x i16> %0, %1869 %5 = sub <8 x i16> %1, %0870 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5871 ret <8 x i16> %6872}873 874define <8 x i16> @absd_int16_slt(<8 x i16>, <8 x i16>) {875; CHECK-LABEL: absd_int16_slt:876; CHECK: # %bb.0:877; CHECK-NEXT: vminsh v4, v2, v3878; CHECK-NEXT: vmaxsh v2, v2, v3879; CHECK-NEXT: vsubuhm v2, v2, v4880; CHECK-NEXT: blr881 %3 = icmp slt <8 x i16> %0, %1882 %4 = sub <8 x i16> %0, %1883 %5 = sub <8 x i16> %1, %0884 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4885 ret <8 x i16> %6886}887 888define <8 x i16> @absd_int16_sle(<8 x i16>, <8 x i16>) {889; CHECK-LABEL: absd_int16_sle:890; CHECK: # %bb.0:891; CHECK-NEXT: vminsh v4, v2, v3892; CHECK-NEXT: vmaxsh v2, v2, v3893; CHECK-NEXT: vsubuhm v2, v2, v4894; CHECK-NEXT: blr895 %3 = icmp sle <8 x i16> %0, %1896 %4 = sub <8 x i16> %0, %1897 %5 = sub <8 x i16> %1, %0898 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4899 ret <8 x i16> %6900}901 902define <16 x i8> @absd_int8_sgt(<16 x i8>, <16 x i8>) {903; CHECK-LABEL: absd_int8_sgt:904; CHECK: # %bb.0:905; CHECK-NEXT: vminsb v4, v2, v3906; CHECK-NEXT: vmaxsb v2, v2, v3907; CHECK-NEXT: vsububm v2, v2, v4908; CHECK-NEXT: blr909 %3 = icmp sgt <16 x i8> %0, %1910 %4 = sub <16 x i8> %0, %1911 %5 = sub <16 x i8> %1, %0912 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5913 ret <16 x i8> %6914}915 916define <16 x i8> @absd_int8_sge(<16 x i8>, <16 x i8>) {917; CHECK-LABEL: absd_int8_sge:918; CHECK: # %bb.0:919; CHECK-NEXT: vminsb v4, v2, v3920; CHECK-NEXT: vmaxsb v2, v2, v3921; CHECK-NEXT: vsububm v2, v2, v4922; CHECK-NEXT: blr923 %3 = icmp sge <16 x i8> %0, %1924 %4 = sub <16 x i8> %0, %1925 %5 = sub <16 x i8> %1, %0926 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5927 ret <16 x i8> %6928}929 930define <16 x i8> @absd_int8_slt(<16 x i8>, <16 x i8>) {931; CHECK-LABEL: absd_int8_slt:932; CHECK: # %bb.0:933; CHECK-NEXT: vminsb v4, v2, v3934; CHECK-NEXT: vmaxsb v2, v2, v3935; CHECK-NEXT: vsububm v2, v2, v4936; CHECK-NEXT: blr937 %3 = icmp slt <16 x i8> %0, %1938 %4 = sub <16 x i8> %0, %1939 %5 = sub <16 x i8> %1, %0940 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4941 ret <16 x i8> %6942}943 944define <16 x i8> @absd_int8_sle(<16 x i8>, <16 x i8>) {945; CHECK-LABEL: absd_int8_sle:946; CHECK: # %bb.0:947; CHECK-NEXT: vminsb v4, v2, v3948; CHECK-NEXT: vmaxsb v2, v2, v3949; CHECK-NEXT: vsububm v2, v2, v4950; CHECK-NEXT: blr951 %3 = icmp sle <16 x i8> %0, %1952 %4 = sub <16 x i8> %0, %1953 %5 = sub <16 x i8> %1, %0954 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4955 ret <16 x i8> %6956}957 958; some cases we are unable to optimize959; check whether goes beyond the scope960define <4 x i32> @absd_int32_ugt_opp(<4 x i32>, <4 x i32>) {961; CHECK-PWR9-LABEL: absd_int32_ugt_opp:962; CHECK-PWR9: # %bb.0:963; CHECK-PWR9-NEXT: vabsduw v2, v2, v3964; CHECK-PWR9-NEXT: vnegw v2, v2965; CHECK-PWR9-NEXT: blr966;967; CHECK-PWR78-LABEL: absd_int32_ugt_opp:968; CHECK-PWR78: # %bb.0:969; CHECK-PWR78-NEXT: vcmpgtuw v4, v2, v3970; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3971; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2972; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4973; CHECK-PWR78-NEXT: blr974 %3 = icmp ugt <4 x i32> %0, %1975 %4 = sub <4 x i32> %0, %1976 %5 = sub <4 x i32> %1, %0977 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4978 ret <4 x i32> %6979}980 981define <2 x i64> @absd_int64_ugt(<2 x i64>, <2 x i64>) {982; CHECK-PWR9-LABEL: absd_int64_ugt:983; CHECK-PWR9: # %bb.0:984; CHECK-PWR9-NEXT: vminud v4, v2, v3985; CHECK-PWR9-NEXT: vmaxud v2, v2, v3986; CHECK-PWR9-NEXT: vsubudm v2, v2, v4987; CHECK-PWR9-NEXT: blr988;989; CHECK-PWR8-LABEL: absd_int64_ugt:990; CHECK-PWR8: # %bb.0:991; CHECK-PWR8-NEXT: vminud v4, v2, v3992; CHECK-PWR8-NEXT: vmaxud v2, v2, v3993; CHECK-PWR8-NEXT: vsubudm v2, v2, v4994; CHECK-PWR8-NEXT: blr995;996; CHECK-PWR7-LABEL: absd_int64_ugt:997; CHECK-PWR7: # %bb.0:998; CHECK-PWR7-NEXT: addi r3, r1, -96999; CHECK-PWR7-NEXT: stxvd2x v2, 0, r31000; CHECK-PWR7-NEXT: addi r3, r1, -801001; CHECK-PWR7-NEXT: stxvd2x v3, 0, r31002; CHECK-PWR7-NEXT: ld r3, -88(r1)1003; CHECK-PWR7-NEXT: ld r4, -72(r1)1004; CHECK-PWR7-NEXT: ld r6, -80(r1)1005; CHECK-PWR7-NEXT: sub r5, r3, r41006; CHECK-PWR7-NEXT: cmpld r3, r41007; CHECK-PWR7-NEXT: li r3, 01008; CHECK-PWR7-NEXT: li r4, -11009; CHECK-PWR7-NEXT: std r5, -56(r1)1010; CHECK-PWR7-NEXT: ld r5, -96(r1)1011; CHECK-PWR7-NEXT: sub r7, r5, r61012; CHECK-PWR7-NEXT: std r7, -64(r1)1013; CHECK-PWR7-NEXT: iselgt r7, r4, r31014; CHECK-PWR7-NEXT: cmpld r5, r61015; CHECK-PWR7-NEXT: std r7, -40(r1)1016; CHECK-PWR7-NEXT: iselgt r3, r4, r31017; CHECK-PWR7-NEXT: addi r4, r1, -641018; CHECK-PWR7-NEXT: std r3, -48(r1)1019; CHECK-PWR7-NEXT: lxvw4x vs0, 0, r41020; CHECK-PWR7-NEXT: addi r4, r1, -481021; CHECK-PWR7-NEXT: lxvw4x vs1, 0, r41022; CHECK-PWR7-NEXT: addi r4, r1, -321023; CHECK-PWR7-NEXT: xxlxor vs0, vs0, vs11024; CHECK-PWR7-NEXT: stxvw4x vs0, 0, r41025; CHECK-PWR7-NEXT: ld r4, -24(r1)1026; CHECK-PWR7-NEXT: sub r4, r7, r41027; CHECK-PWR7-NEXT: std r4, -8(r1)1028; CHECK-PWR7-NEXT: ld r4, -32(r1)1029; CHECK-PWR7-NEXT: sub r3, r3, r41030; CHECK-PWR7-NEXT: std r3, -16(r1)1031; CHECK-PWR7-NEXT: addi r3, r1, -161032; CHECK-PWR7-NEXT: lxvd2x v2, 0, r31033; CHECK-PWR7-NEXT: blr1034 %3 = icmp ugt <2 x i64> %0, %11035 %4 = sub <2 x i64> %0, %11036 %5 = sub <2 x i64> %1, %01037 %6 = select <2 x i1> %3, <2 x i64> %4, <2 x i64> %51038 ret <2 x i64> %61039}1040 1041declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>)1042 1043declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>)1044 1045declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>)1046 1047