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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \4; RUN: | FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \6; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \7; RUN: -enable-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE8 9%0 = type <{ double }>10%1 = type <{ double }>11 12define void @acc_regalloc(ptr %arg, ptr %arg1, ptr %arg2) local_unnamed_addr {13; CHECK-LABEL: acc_regalloc:14; CHECK: # %bb.0: # %bb15; CHECK-NEXT: lwz r3, 0(r3)16; CHECK-NEXT: lxv v0, 0(0)17; CHECK-NEXT: xxlxor v6, v6, v618; CHECK-NEXT: xxlxor v4, v4, v419; CHECK-NEXT: xxlxor v2, v2, v220; CHECK-NEXT: li r6, 121; CHECK-NEXT: li r4, 1622; CHECK-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill23; CHECK-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill24; CHECK-NEXT: extswsli r3, r3, 325; CHECK-NEXT: xvmaddadp v4, v0, v426; CHECK-NEXT: lxvdsx v1, 0, r327; CHECK-NEXT: xvmaddadp v6, v1, v628; CHECK-NEXT: .p2align 429; CHECK-NEXT: .LBB0_1: # %bb930; CHECK-NEXT: #31; CHECK-NEXT: addi r6, r6, 232; CHECK-NEXT: lxv vs1, -64(r5)33; CHECK-NEXT: lxv vs0, 16(0)34; CHECK-NEXT: xxlxor vs7, vs7, vs735; CHECK-NEXT: xxlor vs3, v6, v636; CHECK-NEXT: xxlxor vs2, vs2, vs237; CHECK-NEXT: xxlxor vs12, vs12, vs1238; CHECK-NEXT: lxv vs4, -16(r5)39; CHECK-NEXT: xxlor vs10, v4, v440; CHECK-NEXT: xxlor vs8, v4, v441; CHECK-NEXT: xxlor vs8, v2, v242; CHECK-NEXT: mulld r6, r6, r343; CHECK-NEXT: xvmaddadp vs7, vs0, v144; CHECK-NEXT: xvmuldp vs6, vs0, v245; CHECK-NEXT: xvmaddadp vs3, vs1, v246; CHECK-NEXT: xvmaddadp vs2, vs1, vs247; CHECK-NEXT: xvmaddadp vs12, vs4, vs1248; CHECK-NEXT: xxlor vs0, v2, v249; CHECK-NEXT: lxvdsx v7, r6, r450; CHECK-NEXT: li r6, 051; CHECK-NEXT: xvmaddadp vs7, v2, v252; CHECK-NEXT: xvmaddadp vs6, v2, v253; CHECK-NEXT: xxlor vs14, vs12, vs1254; CHECK-NEXT: xxlor vs12, v2, v255; CHECK-NEXT: xvmuldp v3, vs1, v756; CHECK-NEXT: xvmuldp v5, v0, v757; CHECK-NEXT: xvmuldp vs13, vs4, v758; CHECK-NEXT: xvmuldp vs5, v7, v259; CHECK-NEXT: xxlor vs4, v2, v260; CHECK-NEXT: xxlor vs1, v3, v361; CHECK-NEXT: xxlor vs11, v5, v562; CHECK-NEXT: xxlor vs9, v5, v563; CHECK-NEXT: xxlor vs15, vs13, vs1364; CHECK-NEXT: xxmtacc acc165; CHECK-NEXT: xxmtacc acc066; CHECK-NEXT: xxmtacc acc267; CHECK-NEXT: xxmtacc acc368; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs069; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs070; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs071; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs072; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs073; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs074; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs075; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs076; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs077; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs078; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs079; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs080; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs081; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs082; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs083; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs084; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs085; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs086; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs087; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs088; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs089; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs090; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs091; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs092; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs093; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs094; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs095; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs096; CHECK-NEXT: xxmfacc acc097; CHECK-NEXT: stxv vs1, 0(r3)98; CHECK-NEXT: xxmfacc acc199; CHECK-NEXT: xxmfacc acc2100; CHECK-NEXT: xxmfacc acc3101; CHECK-NEXT: stxv vs9, 32(r3)102; CHECK-NEXT: stxv vs4, 16(0)103; CHECK-NEXT: stxv vs12, 48(0)104; CHECK-NEXT: b .LBB0_1105;106; TRACKLIVE-LABEL: acc_regalloc:107; TRACKLIVE: # %bb.0: # %bb108; TRACKLIVE-NEXT: lwz r3, 0(r3)109; TRACKLIVE-NEXT: lxv v0, 0(0)110; TRACKLIVE-NEXT: xxlxor v6, v6, v6111; TRACKLIVE-NEXT: xxlxor v4, v4, v4112; TRACKLIVE-NEXT: xxlxor v2, v2, v2113; TRACKLIVE-NEXT: li r6, 1114; TRACKLIVE-NEXT: li r4, 16115; TRACKLIVE-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill116; TRACKLIVE-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill117; TRACKLIVE-NEXT: extswsli r3, r3, 3118; TRACKLIVE-NEXT: xvmaddadp v4, v0, v4119; TRACKLIVE-NEXT: lxvdsx v1, 0, r3120; TRACKLIVE-NEXT: xvmaddadp v6, v1, v6121; TRACKLIVE-NEXT: .p2align 4122; TRACKLIVE-NEXT: .LBB0_1: # %bb9123; TRACKLIVE-NEXT: #124; TRACKLIVE-NEXT: addi r6, r6, 2125; TRACKLIVE-NEXT: lxv vs1, -64(r5)126; TRACKLIVE-NEXT: lxv vs0, 16(0)127; TRACKLIVE-NEXT: xxlxor vs7, vs7, vs7128; TRACKLIVE-NEXT: xxlor vs3, v6, v6129; TRACKLIVE-NEXT: xxlxor vs2, vs2, vs2130; TRACKLIVE-NEXT: xxlxor vs12, vs12, vs12131; TRACKLIVE-NEXT: lxv vs4, -16(r5)132; TRACKLIVE-NEXT: xxlor vs10, v4, v4133; TRACKLIVE-NEXT: xxlor vs8, v4, v4134; TRACKLIVE-NEXT: xxlor vs8, v2, v2135; TRACKLIVE-NEXT: mulld r6, r6, r3136; TRACKLIVE-NEXT: xvmaddadp vs7, vs0, v1137; TRACKLIVE-NEXT: xvmuldp vs6, vs0, v2138; TRACKLIVE-NEXT: xvmaddadp vs3, vs1, v2139; TRACKLIVE-NEXT: xvmaddadp vs2, vs1, vs2140; TRACKLIVE-NEXT: xvmaddadp vs12, vs4, vs12141; TRACKLIVE-NEXT: xxlor vs0, v2, v2142; TRACKLIVE-NEXT: lxvdsx v7, r6, r4143; TRACKLIVE-NEXT: li r6, 0144; TRACKLIVE-NEXT: xvmaddadp vs7, v2, v2145; TRACKLIVE-NEXT: xvmaddadp vs6, v2, v2146; TRACKLIVE-NEXT: xxlor vs14, vs12, vs12147; TRACKLIVE-NEXT: xxlor vs12, v2, v2148; TRACKLIVE-NEXT: xvmuldp v3, vs1, v7149; TRACKLIVE-NEXT: xvmuldp v5, v0, v7150; TRACKLIVE-NEXT: xvmuldp vs13, vs4, v7151; TRACKLIVE-NEXT: xvmuldp vs5, v7, v2152; TRACKLIVE-NEXT: xxlor vs4, v2, v2153; TRACKLIVE-NEXT: xxlor vs1, v3, v3154; TRACKLIVE-NEXT: xxlor vs11, v5, v5155; TRACKLIVE-NEXT: xxlor vs9, v5, v5156; TRACKLIVE-NEXT: xxlor vs15, vs13, vs13157; TRACKLIVE-NEXT: xxmtacc acc1158; TRACKLIVE-NEXT: xxmtacc acc0159; TRACKLIVE-NEXT: xxmtacc acc2160; TRACKLIVE-NEXT: xxmtacc acc3161; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0162; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0163; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0164; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0165; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0166; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0167; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0168; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0169; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0170; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0171; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0172; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0173; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0174; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0175; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0176; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0177; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0178; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0179; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0180; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0181; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0182; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0183; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0184; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0185; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0186; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0187; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0188; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0189; TRACKLIVE-NEXT: xxmfacc acc0190; TRACKLIVE-NEXT: stxv vs1, 0(r3)191; TRACKLIVE-NEXT: xxmfacc acc1192; TRACKLIVE-NEXT: xxmfacc acc2193; TRACKLIVE-NEXT: xxmfacc acc3194; TRACKLIVE-NEXT: stxv vs9, 32(r3)195; TRACKLIVE-NEXT: stxv vs4, 16(0)196; TRACKLIVE-NEXT: stxv vs12, 48(0)197; TRACKLIVE-NEXT: b .LBB0_1198bb:199 %i = load i32, ptr %arg, align 4200 %i3 = sext i32 %i to i64201 %i4 = shl nsw i64 %i3, 3202 %i6 = getelementptr i8, ptr %arg1, i64 undef203 %i7 = getelementptr [0 x %1], ptr %arg2, i64 0, i64 -8204 %i8 = getelementptr i8, ptr %i6, i64 undef205 br label %bb9206 207bb9: ; preds = %bb95, %bb208 %i10 = phi i64 [ 1, %bb ], [ 0, %bb95 ]209 %i11 = getelementptr %1, ptr null, i64 2210 %i13 = load <2 x double>, ptr %i11, align 1211 %i14 = add nuw nsw i64 %i10, 2212 %i15 = getelementptr inbounds %1, ptr %i7, i64 undef213 %i17 = load <2 x double>, ptr %i15, align 1214 %i18 = load <2 x double>, ptr null, align 1215 %i19 = getelementptr %1, ptr %i15, i64 6216 %i21 = load <2 x double>, ptr %i19, align 1217 %i22 = load i64, ptr undef, align 8218 %i23 = insertelement <2 x i64> poison, i64 %i22, i32 0219 %i24 = bitcast <2 x i64> %i23 to <2 x double>220 %i25 = shufflevector <2 x double> %i24, <2 x double> undef, <2 x i32> zeroinitializer221 %i26 = mul i64 %i14, %i4222 %i27 = getelementptr i8, ptr null, i64 %i26223 %i29 = getelementptr i8, ptr %i27, i64 16224 %i31 = load i64, ptr %i29, align 8225 %i32 = insertelement <2 x i64> poison, i64 %i31, i32 0226 %i33 = bitcast <2 x i64> %i32 to <2 x double>227 %i34 = shufflevector <2 x double> %i33, <2 x double> undef, <2 x i32> zeroinitializer228 %i35 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> zeroinitializer, <2 x double> %i25, <2 x double> zeroinitializer)229 %i36 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i13, <2 x double> %i25, <2 x double> zeroinitializer)230 %i37 = fmul contract <2 x double> %i13, zeroinitializer231 %i38 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i17, <2 x double> zeroinitializer, <2 x double> %i35)232 %i39 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, <2 x double> %i36)233 %i40 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i17, <2 x double> zeroinitializer, <2 x double> zeroinitializer)234 %i41 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, <2 x double> %i37)235 %i42 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i18, <2 x double> zeroinitializer, <2 x double> zeroinitializer)236 %i43 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i21, <2 x double> zeroinitializer, <2 x double> zeroinitializer)237 %i44 = fmul contract <2 x double> %i17, %i34238 %i45 = fmul contract <2 x double> zeroinitializer, %i34239 %i46 = fmul contract <2 x double> %i18, %i34240 %i47 = fmul contract <2 x double> %i21, %i34241 %i48 = bitcast <2 x double> %i44 to <16 x i8>242 %i49 = bitcast <2 x double> %i40 to <16 x i8>243 %i50 = bitcast <2 x double> %i38 to <16 x i8>244 %i51 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i48, <16 x i8> %i49, <16 x i8> %i50)245 %i52 = bitcast <2 x double> %i45 to <16 x i8>246 %i53 = bitcast <2 x double> %i41 to <16 x i8>247 %i54 = bitcast <2 x double> %i39 to <16 x i8>248 %i55 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i52, <16 x i8> %i53, <16 x i8> %i54)249 %i56 = bitcast <2 x double> %i46 to <16 x i8>250 %i57 = bitcast <2 x double> %i42 to <16 x i8>251 %i58 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i56, <16 x i8> %i57, <16 x i8> %i56)252 %i59 = bitcast <2 x double> %i47 to <16 x i8>253 %i60 = bitcast <2 x double> %i43 to <16 x i8>254 %i61 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i59, <16 x i8> %i60, <16 x i8> %i59)255 %i62 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i51, <256 x i1> undef, <16 x i8> undef)256 %i63 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i55, <256 x i1> undef, <16 x i8> undef)257 %i64 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i58, <256 x i1> undef, <16 x i8> undef)258 %i65 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i61, <256 x i1> undef, <16 x i8> undef)259 %i66 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i62, <256 x i1> undef, <16 x i8> undef)260 %i67 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i63, <256 x i1> undef, <16 x i8> undef)261 %i68 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i64, <256 x i1> undef, <16 x i8> undef)262 %i69 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i65, <256 x i1> undef, <16 x i8> undef)263 %i70 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i66, <256 x i1> undef, <16 x i8> undef)264 %i71 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i67, <256 x i1> undef, <16 x i8> undef)265 %i72 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i68, <256 x i1> undef, <16 x i8> undef)266 %i73 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i69, <256 x i1> undef, <16 x i8> undef)267 %i74 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i70, <256 x i1> undef, <16 x i8> undef)268 %i75 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i71, <256 x i1> undef, <16 x i8> undef)269 %i76 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i72, <256 x i1> undef, <16 x i8> undef)270 %i77 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i73, <256 x i1> undef, <16 x i8> undef)271 %i78 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i74, <256 x i1> undef, <16 x i8> undef)272 %i79 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i75, <256 x i1> undef, <16 x i8> undef)273 %i80 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i76, <256 x i1> undef, <16 x i8> undef)274 %i81 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i77, <256 x i1> undef, <16 x i8> undef)275 br label %bb82276 277bb82: ; preds = %bb82, %bb9278 %i83 = phi <512 x i1> [ %i94, %bb82 ], [ %i81, %bb9 ]279 %i84 = phi <512 x i1> [ %i93, %bb82 ], [ %i80, %bb9 ]280 %i85 = phi <512 x i1> [ %i92, %bb82 ], [ %i79, %bb9 ]281 %i86 = phi <512 x i1> [ %i91, %bb82 ], [ %i78, %bb9 ]282 %i87 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i86, <256 x i1> undef, <16 x i8> undef)283 %i88 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i85, <256 x i1> undef, <16 x i8> undef)284 %i89 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i84, <256 x i1> undef, <16 x i8> undef)285 %i90 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i83, <256 x i1> undef, <16 x i8> undef)286 %i91 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i87, <256 x i1> undef, <16 x i8> undef)287 %i92 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i88, <256 x i1> undef, <16 x i8> undef)288 %i93 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i89, <256 x i1> undef, <16 x i8> undef)289 %i94 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i90, <256 x i1> undef, <16 x i8> undef)290 br i1 undef, label %bb95, label %bb82291 292bb95: ; preds = %bb82293 %i96 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i91)294 %i97 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i96, 2295 %i98 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i92)296 %i99 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i98, 3297 %i100 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i93)298 %i101 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i100, 2299 %i102 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i94)300 %i103 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i102, 3301 %i104 = getelementptr inbounds i8, ptr %i8, i64 undef302 store <16 x i8> %i97, ptr %i104, align 1303 %i106 = getelementptr i8, ptr %i104, i64 32304 store <16 x i8> %i101, ptr %i106, align 1305 %i108 = getelementptr i8, ptr null, i64 16306 store <16 x i8> %i99, ptr %i108, align 1307 %i110 = getelementptr i8, ptr null, i64 48308 store <16 x i8> %i103, ptr %i110, align 1309 br label %bb9310}311 312declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)313declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)314declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)315declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)316 317