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1; RUN: llc -verify-machineinstrs < %s | FileCheck %s2; RUN: llc -mcpu=pwr10 -verify-machineinstrs < %s | FileCheck %s3target datalayout = "E-m:e-i64:64-n32:64"4target triple = "powerpc64-unknown-linux-gnu"5 6; CHECK-LABEL: test:7; CHECK: {{^}}.L[[test_BEGIN:.*]]:{{$}}8 9; CHECK-LABEL: property_access1:10; CHECK: {{^}}.L[[property_access1_BEGIN:.*]]:{{$}}11 12; CHECK-LABEL: property_access2:13; CHECK: {{^}}.L[[property_access2_BEGIN:.*]]:{{$}}14 15; CHECK-LABEL: property_access3:16; CHECK: {{^}}.L[[property_access3_BEGIN:.*]]:{{$}}17 18; CHECK-LABEL: anyreg_test1:19; CHECK: {{^}}.L[[anyreg_test1_BEGIN:.*]]:{{$}}20 21; CHECK-LABEL: anyreg_test2:22; CHECK: {{^}}.L[[anyreg_test2_BEGIN:.*]]:{{$}}23 24; CHECK-LABEL: patchpoint_spilldef:25; CHECK: {{^}}.L[[patchpoint_spilldef_BEGIN:.*]]:{{$}}26 27; CHECK-LABEL: patchpoint_spillargs:28; CHECK: {{^}}.L[[patchpoint_spillargs_BEGIN:.*]]:{{$}}29 30 31; Stackmap Header: no constants - 6 callsites32; CHECK-LABEL: .section .llvm_stackmaps33; CHECK-NEXT: __LLVM_StackMaps:34; Header35; CHECK-NEXT: .byte 336; CHECK-NEXT: .byte 037; CHECK-NEXT: .short 038; Num Functions39; CHECK-NEXT: .long 840; Num LargeConstants41; CHECK-NEXT: .long 042; Num Callsites43; CHECK-NEXT: .long 844 45; Functions and stack size46; CHECK-NEXT: .quad test47; CHECK-NEXT: .quad 12848; CHECK-NEXT: .quad 149; CHECK-NEXT: .quad property_access150; CHECK-NEXT: .quad 12851; CHECK-NEXT: .quad 152; CHECK-NEXT: .quad property_access253; CHECK-NEXT: .quad 12854; CHECK-NEXT: .quad 155; CHECK-NEXT: .quad property_access356; CHECK-NEXT: .quad 12857; CHECK-NEXT: .quad 158; CHECK-NEXT: .quad anyreg_test159; CHECK-NEXT: .quad 14460; CHECK-NEXT: .quad 161; CHECK-NEXT: .quad anyreg_test262; CHECK-NEXT: .quad 14463; CHECK-NEXT: .quad 164; CHECK-NEXT: .quad patchpoint_spilldef65; CHECK-NEXT: .quad 25666; CHECK-NEXT: .quad 167; CHECK-NEXT: .quad patchpoint_spillargs68; CHECK-NEXT: .quad 28869; CHECK-NEXT: .quad 170 71 72; test73; CHECK: .long .L{{.*}}-.L[[test_BEGIN]]74; CHECK-NEXT: .short 075; 3 locations76; CHECK-NEXT: .short 377; Loc 0: Register78; CHECK-NEXT: .byte 179; CHECK-NEXT: .byte 080; CHECK-NEXT: .short 481; CHECK-NEXT: .short {{[0-9]+}}82; CHECK-NEXT: .short 083; CHECK-NEXT: .long 084; Loc 1: Register85; CHECK-NEXT: .byte 186; CHECK-NEXT: .byte 087; CHECK-NEXT: .short 488; CHECK-NEXT: .short {{[0-9]+}}89; CHECK-NEXT: .short 090; CHECK-NEXT: .long 091; Loc 2: Constant 392; CHECK-NEXT: .byte 493; CHECK-NEXT: .byte 094; CHECK-NEXT: .short 895; CHECK-NEXT: .short 096; CHECK-NEXT: .short 097; CHECK-NEXT: .long 398define i64 @test() nounwind ssp uwtable {99entry:100 call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 40, ptr null, i32 2, i32 1, i32 2, i64 3)101 ret i64 0102}103 104; property access 1 - %obj is an anyreg call argument and should therefore be in a register105; CHECK: .long .L{{.*}}-.L[[property_access1_BEGIN]]106; CHECK-NEXT: .short 0107; 2 locations108; CHECK-NEXT: .short 2109; Loc 0: Register <-- this is the return register110; CHECK-NEXT: .byte 1111; CHECK-NEXT: .byte 0112; CHECK-NEXT: .short 8113; CHECK-NEXT: .short {{[0-9]+}}114; CHECK-NEXT: .short 0115; CHECK-NEXT: .long 0116; Loc 1: Register117; CHECK-NEXT: .byte 1118; CHECK-NEXT: .byte 0119; CHECK-NEXT: .short 8120; CHECK-NEXT: .short {{[0-9]+}}121; CHECK-NEXT: .short 0122; CHECK-NEXT: .long 0123define i64 @property_access1(ptr %obj) nounwind ssp uwtable {124entry:125 %f = inttoptr i64 281474417671919 to ptr126 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 40, ptr %f, i32 1, ptr %obj)127 ret i64 %ret128}129 130; property access 2 - %obj is an anyreg call argument and should therefore be in a register131; CHECK: .long .L{{.*}}-.L[[property_access2_BEGIN]]132; CHECK-NEXT: .short 0133; 2 locations134; CHECK-NEXT: .short 2135; Loc 0: Register <-- this is the return register136; CHECK-NEXT: .byte 1137; CHECK-NEXT: .byte 0138; CHECK-NEXT: .short 8139; CHECK-NEXT: .short {{[0-9]+}}140; CHECK-NEXT: .short 0141; CHECK-NEXT: .long 0142; Loc 1: Register143; CHECK-NEXT: .byte 1144; CHECK-NEXT: .byte 0145; CHECK-NEXT: .short 8146; CHECK-NEXT: .short {{[0-9]+}}147; CHECK-NEXT: .short 0148; CHECK-NEXT: .long 0149define i64 @property_access2() nounwind ssp uwtable {150entry:151 %obj = alloca i64, align 8152 %f = inttoptr i64 281474417671919 to ptr153 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, ptr %f, i32 1, ptr %obj)154 ret i64 %ret155}156 157; property access 3 - %obj is a frame index158; CHECK: .long .L{{.*}}-.L[[property_access3_BEGIN]]159; CHECK-NEXT: .short 0160; 2 locations161; CHECK-NEXT: .short 2162; Loc 0: Register <-- this is the return register163; CHECK-NEXT: .byte 1164; CHECK-NEXT: .byte 0165; CHECK-NEXT: .short 8166; CHECK-NEXT: .short {{[0-9]+}}167; CHECK-NEXT: .short 0168; CHECK-NEXT: .long 0169; Loc 1: Direct FP - 8170; CHECK-NEXT: .byte 2171; CHECK-NEXT: .byte 0172; CHECK-NEXT: .short 8173; CHECK-NEXT: .short 31174; CHECK-NEXT: .short 0175; CHECK-NEXT: .long 112176define i64 @property_access3() nounwind ssp uwtable {177entry:178 %obj = alloca i64, align 8179 %f = inttoptr i64 281474417671919 to ptr180 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 40, ptr %f, i32 0, ptr %obj)181 ret i64 %ret182}183 184; anyreg_test1185; CHECK: .long .L{{.*}}-.L[[anyreg_test1_BEGIN]]186; CHECK-NEXT: .short 0187; 14 locations188; CHECK-NEXT: .short 14189; Loc 0: Register <-- this is the return register190; CHECK-NEXT: .byte 1191; CHECK-NEXT: .byte 0192; CHECK-NEXT: .short 8193; CHECK-NEXT: .short {{[0-9]+}}194; CHECK-NEXT: .short 0195; CHECK-NEXT: .long 0196; Loc 1: Register197; CHECK-NEXT: .byte 1198; CHECK-NEXT: .byte 0199; CHECK-NEXT: .short 8200; CHECK-NEXT: .short {{[0-9]+}}201; CHECK-NEXT: .short 0202; CHECK-NEXT: .long 0203; Loc 2: Register204; CHECK-NEXT: .byte 1205; CHECK-NEXT: .byte 0206; CHECK-NEXT: .short 8207; CHECK-NEXT: .short {{[0-9]+}}208; CHECK-NEXT: .short 0209; CHECK-NEXT: .long 0210; Loc 3: Register211; CHECK-NEXT: .byte 1212; CHECK-NEXT: .byte 0213; CHECK-NEXT: .short 8214; CHECK-NEXT: .short {{[0-9]+}}215; CHECK-NEXT: .short 0216; CHECK-NEXT: .long 0217; Loc 4: Register218; CHECK-NEXT: .byte 1219; CHECK-NEXT: .byte 0220; CHECK-NEXT: .short 8221; CHECK-NEXT: .short {{[0-9]+}}222; CHECK-NEXT: .short 0223; CHECK-NEXT: .long 0224; Loc 5: Register225; CHECK-NEXT: .byte 1226; CHECK-NEXT: .byte 0227; CHECK-NEXT: .short 8228; CHECK-NEXT: .short {{[0-9]+}}229; CHECK-NEXT: .short 0230; CHECK-NEXT: .long 0231; Loc 6: Register232; CHECK-NEXT: .byte 1233; CHECK-NEXT: .byte 0234; CHECK-NEXT: .short 8235; CHECK-NEXT: .short {{[0-9]+}}236; CHECK-NEXT: .short 0237; CHECK-NEXT: .long 0238; Loc 7: Register239; CHECK-NEXT: .byte 1240; CHECK-NEXT: .byte 0241; CHECK-NEXT: .short 8242; CHECK-NEXT: .short {{[0-9]+}}243; CHECK-NEXT: .short 0244; CHECK-NEXT: .long 0245; Loc 8: Register246; CHECK-NEXT: .byte 1247; CHECK-NEXT: .byte 0248; CHECK-NEXT: .short 8249; CHECK-NEXT: .short {{[0-9]+}}250; CHECK-NEXT: .short 0251; CHECK-NEXT: .long 0252; Loc 9: Register253; CHECK-NEXT: .byte 1254; CHECK-NEXT: .byte 0255; CHECK-NEXT: .short 8256; CHECK-NEXT: .short {{[0-9]+}}257; CHECK-NEXT: .short 0258; CHECK-NEXT: .long 0259; Loc 10: Register260; CHECK-NEXT: .byte 1261; CHECK-NEXT: .byte 0262; CHECK-NEXT: .short 8263; CHECK-NEXT: .short {{[0-9]+}}264; CHECK-NEXT: .short 0265; CHECK-NEXT: .long 0266; Loc 11: Register267; CHECK-NEXT: .byte 1268; CHECK-NEXT: .byte 0269; CHECK-NEXT: .short 8270; CHECK-NEXT: .short {{[0-9]+}}271; CHECK-NEXT: .short 0272; CHECK-NEXT: .long 0273; Loc 12: Register274; CHECK-NEXT: .byte 1275; CHECK-NEXT: .byte 0276; CHECK-NEXT: .short 8277; CHECK-NEXT: .short {{[0-9]+}}278; CHECK-NEXT: .short 0279; CHECK-NEXT: .long 0280; Loc 13: Register281; CHECK-NEXT: .byte 1282; CHECK-NEXT: .byte 0283; CHECK-NEXT: .short 8284; CHECK-NEXT: .short {{[0-9]+}}285; CHECK-NEXT: .short 0286; CHECK-NEXT: .long 0287define i64 @anyreg_test1(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {288entry:289 %f = inttoptr i64 281474417671919 to ptr290 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 40, ptr %f, i32 13, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)291 ret i64 %ret292}293 294; anyreg_test2295; CHECK: .long .L{{.*}}-.L[[anyreg_test2_BEGIN]]296; CHECK-NEXT: .short 0297; 14 locations298; CHECK-NEXT: .short 14299; Loc 0: Register <-- this is the return register300; CHECK-NEXT: .byte 1301; CHECK-NEXT: .byte 0302; CHECK-NEXT: .short 8303; CHECK-NEXT: .short {{[0-9]+}}304; CHECK-NEXT: .short 0305; CHECK-NEXT: .long 0306; Loc 1: Register307; CHECK-NEXT: .byte 1308; CHECK-NEXT: .byte 0309; CHECK-NEXT: .short 8310; CHECK-NEXT: .short {{[0-9]+}}311; CHECK-NEXT: .short 0312; CHECK-NEXT: .long 0313; Loc 2: Register314; CHECK-NEXT: .byte 1315; CHECK-NEXT: .byte 0316; CHECK-NEXT: .short 8317; CHECK-NEXT: .short {{[0-9]+}}318; CHECK-NEXT: .short 0319; CHECK-NEXT: .long 0320; Loc 3: Register321; CHECK-NEXT: .byte 1322; CHECK-NEXT: .byte 0323; CHECK-NEXT: .short 8324; CHECK-NEXT: .short {{[0-9]+}}325; CHECK-NEXT: .short 0326; CHECK-NEXT: .long 0327; Loc 4: Register328; CHECK-NEXT: .byte 1329; CHECK-NEXT: .byte 0330; CHECK-NEXT: .short 8331; CHECK-NEXT: .short {{[0-9]+}}332; CHECK-NEXT: .short 0333; CHECK-NEXT: .long 0334; Loc 5: Register335; CHECK-NEXT: .byte 1336; CHECK-NEXT: .byte 0337; CHECK-NEXT: .short 8338; CHECK-NEXT: .short {{[0-9]+}}339; CHECK-NEXT: .short 0340; CHECK-NEXT: .long 0341; Loc 6: Register342; CHECK-NEXT: .byte 1343; CHECK-NEXT: .byte 0344; CHECK-NEXT: .short 8345; CHECK-NEXT: .short {{[0-9]+}}346; CHECK-NEXT: .short 0347; CHECK-NEXT: .long 0348; Loc 7: Register349; CHECK-NEXT: .byte 1350; CHECK-NEXT: .byte 0351; CHECK-NEXT: .short 8352; CHECK-NEXT: .short {{[0-9]+}}353; CHECK-NEXT: .short 0354; CHECK-NEXT: .long 0355; Loc 8: Register356; CHECK-NEXT: .byte 1357; CHECK-NEXT: .byte 0358; CHECK-NEXT: .short 8359; CHECK-NEXT: .short {{[0-9]+}}360; CHECK-NEXT: .short 0361; CHECK-NEXT: .long 0362; Loc 9: Register363; CHECK-NEXT: .byte 1364; CHECK-NEXT: .byte 0365; CHECK-NEXT: .short 8366; CHECK-NEXT: .short {{[0-9]+}}367; CHECK-NEXT: .short 0368; CHECK-NEXT: .long 0369; Loc 10: Register370; CHECK-NEXT: .byte 1371; CHECK-NEXT: .byte 0372; CHECK-NEXT: .short 8373; CHECK-NEXT: .short {{[0-9]+}}374; CHECK-NEXT: .short 0375; CHECK-NEXT: .long 0376; Loc 11: Register377; CHECK-NEXT: .byte 1378; CHECK-NEXT: .byte 0379; CHECK-NEXT: .short 8380; CHECK-NEXT: .short {{[0-9]+}}381; CHECK-NEXT: .short 0382; CHECK-NEXT: .long 0383; Loc 12: Register384; CHECK-NEXT: .byte 1385; CHECK-NEXT: .byte 0386; CHECK-NEXT: .short 8387; CHECK-NEXT: .short {{[0-9]+}}388; CHECK-NEXT: .short 0389; CHECK-NEXT: .long 0390; Loc 13: Register391; CHECK-NEXT: .byte 1392; CHECK-NEXT: .byte 0393; CHECK-NEXT: .short 8394; CHECK-NEXT: .short {{[0-9]+}}395; CHECK-NEXT: .short 0396; CHECK-NEXT: .long 0397define i64 @anyreg_test2(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {398entry:399 %f = inttoptr i64 281474417671919 to ptr400 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, ptr %f, i32 8, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)401 ret i64 %ret402}403 404; Test spilling the return value of an anyregcc call.405;406; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"407;408; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]]409; CHECK-NEXT: .short 0410; CHECK-NEXT: .short 3411; Loc 0: Register (some register that will be spilled to the stack)412; CHECK-NEXT: .byte 1413; CHECK-NEXT: .byte 0414; CHECK-NEXT: .short 8415; CHECK-NEXT: .short {{[0-9]+}}416; CHECK-NEXT: .short 0417; CHECK-NEXT: .long 0418; Loc 1: Register419; CHECK-NEXT: .byte 1420; CHECK-NEXT: .byte 0421; CHECK-NEXT: .short 8422; CHECK-NEXT: .short {{[0-9]+}}423; CHECK-NEXT: .short 0424; CHECK-NEXT: .long 0425; Loc 1: Register426; CHECK-NEXT: .byte 1427; CHECK-NEXT: .byte 0428; CHECK-NEXT: .short 8429; CHECK-NEXT: .short {{[0-9]+}}430; CHECK-NEXT: .short 0431; CHECK-NEXT: .long 0432define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {433entry:434 %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 40, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2)435 tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17436},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind437 ret i64 %result438}439 440; Test spilling the arguments of an anyregcc call.441;442; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled443;444; CHECK: .long .L{{.*}}-.L[[patchpoint_spillargs_BEGIN]]445; CHECK-NEXT: .short 0446; CHECK-NEXT: .short 5447; Loc 0: Return a register448; CHECK-NEXT: .byte 1449; CHECK-NEXT: .byte 0450; CHECK-NEXT: .short 8451; CHECK-NEXT: .short {{[0-9]+}}452; CHECK-NEXT: .short 0453; CHECK-NEXT: .long 0454; Loc 1: Arg0 in a Register455; CHECK-NEXT: .byte 1456; CHECK-NEXT: .byte 0457; CHECK-NEXT: .short 8458; CHECK-NEXT: .short {{[0-9]+}}459; CHECK-NEXT: .short 0460; CHECK-NEXT: .long 0461; Loc 2: Arg1 in a Register462; CHECK-NEXT: .byte 1463; CHECK-NEXT: .byte 0464; CHECK-NEXT: .short 8465; CHECK-NEXT: .short {{[0-9]+}}466; CHECK-NEXT: .short 0467; CHECK-NEXT: .long 0468; Loc 3: Arg2 spilled to FP -96469; CHECK-NEXT: .byte 3470; CHECK-NEXT: .byte 0471; CHECK-NEXT: .short 8472; CHECK-NEXT: .short 31473; CHECK-NEXT: .short 0474; CHECK-NEXT: .long 128475; Loc 4: Arg3 spilled to FP - 88476; CHECK-NEXT: .byte 3477; CHECK-NEXT: .byte 0478; CHECK-NEXT: .short 8479; CHECK-NEXT: .short 31480; CHECK-NEXT: .short 0481; CHECK-NEXT: .long 136482define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {483entry:484 tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17485},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind486 %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 40, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)487 ret i64 %result488}489 490declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)491declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)492