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1; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \2; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE \3; RUN: --implicit-check-not xxswapd4 5; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \6; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE7 8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \9; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE10 11; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \12; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX13 14; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \15; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX16 17; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \18; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \19; RUN: --implicit-check-not xxswapd20 21; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \22; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX23 24; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \25; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX26 27; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \28; RUN: -mcpu=pwr8 -mattr=-vsx < %s | \29; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd30 31; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \32; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \33; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd34 35; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \36; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s -check-prefix=CHECK-P937 38; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \39; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \40; RUN: --implicit-check-not xxswapd41 42; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \43; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX44 45; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \46; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \47; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd48 49@x = common global <1 x i128> zeroinitializer, align 1650@y = common global <1 x i128> zeroinitializer, align 1651@a = common global i128 zeroinitializer, align 1652@b = common global i128 zeroinitializer, align 1653 54; VSX:55; %a is passed in register 3456; The value of 1 is stored in the TOC.57; On LE, ensure the value of 1 is swapped before being used (using xxswapd).58; VMX (no VSX): 59; %a is passed in register 260; The value of 1 is stored in the TOC.61; No swaps are necessary when using P8 Vector instructions on LE62define <1 x i128> @v1i128_increment_by_one(<1 x i128> %a) nounwind {63 %tmp = add <1 x i128> %a, <i128 1>64 ret <1 x i128> %tmp 65 66; FIXME: Seems a 128-bit literal is materialized by loading from the TOC. There67; should be a better way of doing this.68 69; CHECK-LE-LABEL: @v1i128_increment_by_one70; CHECK-LE: lxvd2x [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}71; CHECK-LE: xxswapd 35, [[VAL]]72; CHECK-LE: vadduqm 2, 2, 373; CHECK-LE: blr74 75; CHECK-P9-LABEL: @v1i128_increment_by_one76; The below FIXME is due to the lowering for BUILD_VECTOR that will be fixed77; in a subsequent patch.78; FIXME: li [[R1:r[0-9]+]], 179; FIXME: li [[R2:r[0-9]+]], 080; FIXME: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]]81; CHECK-P9: lxv [[V1:v[0-9]+]]82; CHECK-P9: vadduqm v2, v2, [[V1]]83; CHECK-P9: blr84 85; CHECK-BE-LABEL: @v1i128_increment_by_one86; CHECK-BE: lxvd2x 35, {{[0-9]+}}, {{[0-9]+}}87; CHECK-BE-NOT: xxswapd 88; CHECK-BE: vadduqm 2, 2, 3 89; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}90; CHECK-BE: blr91 92; CHECK-NOVSX-LABEL: @v1i128_increment_by_one93; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}94; CHECK-NOVSX-NOT: stxvd2x {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}95; CHECK-NOVSX: lvx [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}96; CHECK-NOVSX-NOT: lxvd2x {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}97; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}98; CHECK-NOVSX: vadduqm 2, 2, [[VAL]]99; CHECK-NOVSX: blr100}101 102; VSX:103; %a is passed in register 34104; %b is passed in register 35105; No swaps are necessary when using P8 Vector instructions on LE106; VMX (no VSX):107; %a is passewd in register 2108; %b is passed in register 3109; On LE, do not need to swap contents of 2 and 3 because the lvx/stvx 110; instructions no not swap elements111define <1 x i128> @v1i128_increment_by_val(<1 x i128> %a, <1 x i128> %b) nounwind {112 %tmp = add <1 x i128> %a, %b113 ret <1 x i128> %tmp114 115; CHECK-LE-LABEL: @v1i128_increment_by_val116; CHECK-LE-NOT: xxswapd117; CHECK-LE: adduqm 2, 2, 3118; CHECK-LE: blr119 120; CHECK-BE-LABEL: @v1i128_increment_by_val121; CHECK-BE-NOT: xxswapd {{[0-9]+}}, 34122; CHECK-BE-NOT: xxswapd {{[0-9]+}}, 35123; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}124; CHECK-BE: adduqm 2, 2, 3125; CHECK-BE: blr126 127; CHECK-NOVSX-LABEL: @v1i128_increment_by_val128; CHECK-NOVSX-NOT: xxswapd 34, {{[0-9]+}}129; CHECK-NOVSX: adduqm 2, 2, 3130; CHECK-NOVSX: blr131}132 133; Little Endian (VSX and VMX):134; Lower 64-bits of %a are passed in register 3135; Upper 64-bits of %a are passed in register 4136; Increment lower 64-bits using addic (immediate value of 1)137; Increment upper 64-bits using add zero extended138; Results are placed in registers 3 and 4139; Big Endian (VSX and VMX)140; Lower 64-bits of %a are passed in register 4141; Upper 64-bits of %a are passed in register 3142; Increment lower 64-bits using addic (immediate value of 1)143; Increment upper 64-bits using add zero extended144; Results are placed in registers 3 and 4145define i128 @i128_increment_by_one(i128 %a) nounwind {146 %tmp = add i128 %a, 1147 ret i128 %tmp148; CHECK-LE-LABEL: @i128_increment_by_one149; CHECK-LE: addic 3, 3, 1150; CHECK-LE-NEXT: addze 4, 4151; CHECK-LE: blr152 153; CHECK-BE-LABEL: @i128_increment_by_one154; CHECK-BE: addic 4, 4, 1155; CHECK-BE-NEXT: addze 3, 3156; CHECK-BE: blr157 158; CHECK-LE-NOVSX-LABEL: @i128_increment_by_one159; CHECK-LE-NOVSX: addic 3, 3, 1160; CHECK-LE-NOVSX-NEXT: addze 4, 4161; CHECK-LE-NOVSX: blr162 163; CHECK-BE-NOVSX-LABEL: @i128_increment_by_one164; CHECK-BE-NOVSX: addic 4, 4, 1165; CHECK-BE-NOVSX-NEXT: addze 3, 3166; CHECK-BE-NOVSX: blr167}168 169; Little Endian (VSX and VMX):170; Lower 64-bits of %a are passed in register 3171; Upper 64-bits of %a are passed in register 4172; Lower 64-bits of %b are passed in register 5173; Upper 64-bits of %b are passed in register 6174; Add the lower 64-bits using addc on registers 3 and 5175; Add the upper 64-bits using adde on registers 4 and 6176; Registers 3 and 4 should hold the result177; Big Endian (VSX and VMX):178; Upper 64-bits of %a are passed in register 3179; Lower 64-bits of %a are passed in register 4180; Upper 64-bits of %b are passed in register 5181; Lower 64-bits of %b are passed in register 6182; Add the lower 64-bits using addc on registers 4 and 6183; Add the upper 64-bits using adde on registers 3 and 5184; Registers 3 and 4 should hold the result185define i128 @i128_increment_by_val(i128 %a, i128 %b) nounwind {186 %tmp = add i128 %a, %b187 ret i128 %tmp188; CHECK-LE-LABEL: @i128_increment_by_val189; CHECK-LE: addc 3, 3, 5190; CHECK-LE-NEXT: adde 4, 4, 6191; CHECK-LE: blr192 193; CHECK-BE-LABEL: @i128_increment_by_val194; CHECK-BE: addc 4, 4, 6195; CHECK-BE-NEXT: adde 3, 3, 5196; CHECK-BE: blr197 198; CHECK-LE-NOVSX-LABEL: @i128_increment_by_val199; CHECK-LE-NOVSX: addc 3, 3, 5200; CHECK-LE-NOVSX-NEXT: adde 4, 4, 6201; CHECK-LE-NOVSX: blr202 203; CHECK-BE-NOVSX-LABEL: @i128_increment_by_val204; CHECK-BE-NOVSX: addc 4, 4, 6205; CHECK-BE-NOVSX-NEXT: adde 3, 3, 5206; CHECK-BE-NOVSX: blr207}208 209 210; Callsites for the routines defined above. 211; Ensure the parameters are loaded in the same order that is expected by the 212; callee. See comments for individual functions above for details on registers213; used for parameters.214define <1 x i128> @call_v1i128_increment_by_one() nounwind {215 %tmp = load <1 x i128>, ptr @x, align 16216 %ret = call <1 x i128> @v1i128_increment_by_one(<1 x i128> %tmp)217 ret <1 x i128> %ret218 219; CHECK-LE-LABEL: @call_v1i128_increment_by_one220; CHECK-LE: lxvd2x [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}221; CHECK-LE: xxswapd 34, [[VAL]]222; CHECK-LE: bl v1i128_increment_by_one223; CHECK-LE: blr224 225; CHECK-P9-LABEL: @call_v1i128_increment_by_one226; CHECK-P9: lxv227; CHECK-P9: bl {{.?}}v1i128_increment_by_one228; CHECK-P9: blr229 230; CHECK-BE-LABEL: @call_v1i128_increment_by_one231; CHECK-BE: lxvw4x 34, {{[0-9]+}}, {{[0-9]+}}232; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}233; CHECK-BE: bl {{.?}}v1i128_increment_by_one234; CHECK-BE: blr235 236; CHECK-NOVSX-LABEL: @call_v1i128_increment_by_one237; CHECK-NOVSX: lvx 2, {{[0-9]+}}, {{[0-9]+}}238; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}239; CHECK-NOVSX: bl {{.?}}v1i128_increment_by_one240; CHECK-NOVSX: blr241}242 243define <1 x i128> @call_v1i128_increment_by_val() nounwind {244 %tmp = load <1 x i128>, ptr @x, align 16245 %tmp2 = load <1 x i128>, ptr @y, align 16246 %ret = call <1 x i128> @v1i128_increment_by_val(<1 x i128> %tmp, <1 x i128> %tmp2)247 ret <1 x i128> %ret248 249; CHECK-LE-LABEL: @call_v1i128_increment_by_val250; CHECK-LE: lxvd2x [[VAL1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}251; CHECK-LE-DAG: lxvd2x [[VAL2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}252; CHECK-LE-DAG: xxswapd 34, [[VAL1]]253; CHECK-LE: xxswapd 35, [[VAL2]]254; CHECK-LE: bl v1i128_increment_by_val255; CHECK-LE: blr256 257; CHECK-P9-LABEL: @call_v1i128_increment_by_val258; CHECK-P9-DAG: lxv v2259; CHECK-P9-DAG: lxv v3260; CHECK-P9: bl {{.?}}v1i128_increment_by_val261; CHECK-P9: blr262 263; CHECK-BE-LABEL: @call_v1i128_increment_by_val264 265 266; CHECK-BE-DAG: lxvw4x 35, {{[0-9]+}}, {{[0-9]+}}267; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}268; CHECK-BE-NOT: xxswapd 35, {{[0-9]+}}269; CHECK-BE: bl {{.?}}v1i128_increment_by_val270; CHECK-BE: blr271 272; CHECK-NOVSX-LABEL: @call_v1i128_increment_by_val273; CHECK-NOVSX-DAG: lvx 2, {{[0-9]+}}, {{[0-9]+}}274; CHECK-NOVSX-DAG: lvx 3, {{[0-9]+}}, {{[0-9]+}}275; CHECK-NOVSX-NOT: xxswapd 34, {{[0-9]+}}276; CHECK-NOVSX-NOT: xxswapd 35, {{[0-9]+}}277; CHECK-NOVSX: bl {{.?}}v1i128_increment_by_val278; CHECK-NOVSX: blr279 280}281 282define i128 @call_i128_increment_by_one() nounwind {283 %tmp = load i128, ptr @a, align 16284 %ret = call i128 @i128_increment_by_one(i128 %tmp)285 ret i128 %ret286; %ret4 = call i128 @i128_increment_by_val(i128 %tmp2, i128 %tmp2)287; CHECK-LE-LABEL: @call_i128_increment_by_one288; CHECK-LE-DAG: ld 3, 0([[BASEREG:[0-9]+]])289; CHECK-LE-DAG: ld 4, 8([[BASEREG]])290; CHECK-LE: bl i128_increment_by_one291; CHECK-LE: blr292 293; CHECK-BE-LABEL: @call_i128_increment_by_one294; CHECK-BE-DAG: ld 3, 0([[BASEREG:[0-9]+]])295; CHECK-BE-DAG: ld 4, 8([[BASEREG]])296; CHECK-BE: bl {{.?}}i128_increment_by_one297; CHECK-BE: blr298 299; CHECK-NOVSX-LABEL: @call_i128_increment_by_one300; CHECK-NOVSX-DAG: ld 3, 0([[BASEREG:[0-9]+]])301; CHECK-NOVSX-DAG: ld 4, 8([[BASEREG]])302; CHECK-NOVSX: bl {{.?}}i128_increment_by_one303; CHECK-NOVSX: blr304}305 306define i128 @call_i128_increment_by_val() nounwind {307 %tmp = load i128, ptr @a, align 16308 %tmp2 = load i128, ptr @b, align 16309 %ret = call i128 @i128_increment_by_val(i128 %tmp, i128 %tmp2)310 ret i128 %ret311; CHECK-LE-LABEL: @call_i128_increment_by_val312; CHECK-LE-DAG: ld 3, 0([[P1BASEREG:[0-9]+]])313; CHECK-LE-DAG: ld 4, 8([[P1BASEREG]])314; CHECK-LE-DAG: ld 5, 0([[P2BASEREG:[0-9]+]])315; CHECK-LE-DAG: ld 6, 8([[P2BASEREG]])316; CHECK-LE: bl i128_increment_by_val317; CHECK-LE: blr318 319; CHECK-BE-LABEL: @call_i128_increment_by_val320; CHECK-BE-DAG: ld 3, 0([[P1BASEREG:[0-9]+]])321; CHECK-BE-DAG: ld 4, 8([[P1BASEREG]])322; CHECK-BE-DAG: ld 5, 0([[P2BASEREG:[0-9]+]])323; CHECK-BE-DAG: ld 6, 8([[P2BASEREG]])324; CHECK-BE: bl {{.?}}i128_increment_by_val325; CHECK-BE: blr326 327; CHECK-NOVSX-LABEL: @call_i128_increment_by_val328; CHECK-NOVSX-DAG: ld 3, 0([[P1BASEREG:[0-9]+]])329; CHECK-NOVSX-DAG: ld 4, 8([[P1BASEREG]])330; CHECK-NOVSX-DAG: ld 5, 0([[P2BASEREG:[0-9]+]])331; CHECK-NOVSX-DAG: ld 6, 8([[P2BASEREG]])332; CHECK-NOVSX: bl {{.?}}i128_increment_by_val333; CHECK-NOVSX: blr334}335 336define i128 @callee_i128_split(i32 %i, i128 %i1280, i32 %i4, i32 %i5,337 i32 %i6, i32 %i7, i128 %i1281, i32 %i8, i128 %i1282){338entry:339 %tmp = add i128 %i1280, %i1281340 %tmp1 = add i128 %tmp, %i1282341 342 ret i128 %tmp1343}344; CHECK-LE-LABEL: @callee_i128_split345; CHECK-LE-DAG: ld [[TMPREG:[0-9]+]], [[OFFSET:[0-9]+]](1)346; CHECK-LE-DAG: addc [[TMPREG2:[0-9]+]], 4, 10347; CHECK-LE-DAG: adde [[TMPREG3:[0-9]+]], 5, [[TMPREG]]348 349; CHECK-LE-DAG: ld [[TMPREG4:[0-9]+]], [[OFFSET2:[0-9]+]](1)350; CHECK-LE-DAG: ld [[TMPREG5:[0-9]+]], [[OFFSET3:[0-9]+]](1)351; CHECK-LE-DAG: addc 3, [[TMPREG2]], [[TMPREG4]]352; CHECK-LE-DAG: adde 4, [[TMPREG3]], [[TMPREG5]]353 354; CHECK-BE-LABEL: @callee_i128_split355; CHECK-BE-DAG: ld [[TMPREG:[0-9]+]], [[OFFSET:[0-9]+]](1)356; CHECK-BE-DAG: addc [[TMPREG3:[0-9]+]], 5, [[TMPREG]]357; CHECK-BE-DAG: adde [[TMPREG2:[0-9]+]], 4, 10358 359; CHECK-BE-DAG: ld [[TMPREG4:[0-9]+]], [[OFFSET2:[0-9]+]](1)360; CHECK-BE-DAG: ld [[TMPREG5:[0-9]+]], [[OFFSET3:[0-9]+]](1)361; CHECK-BE-DAG: addc 4, [[TMPREG3]], [[TMPREG4]]362; CHECK-BE-DAG: adde 3, [[TMPREG2]], [[TMPREG5]]363 364define i128 @i128_split() {365entry:366 %0 = load i128, ptr @a, align 16367 %1 = load i128, ptr @b, align 16368 %call = tail call i128 @callee_i128_split(i32 1, i128 %0, i32 4, i32 5,369 i32 6, i32 7, i128 %1, i32 8, i128 9)370 ret i128 %call371}372 373; CHECK-LE-LABEL: @i128_split374; CHECK-LE-DAG: li 3, 1375; CHECK-LE-DAG: ld 4, 0([[P2BASEREG:[0-9]+]])376; CHECK-LE-DAG: ld 5, 8([[P2BASEREG]])377; CHECK-LE-DAG: li 6, 4378; CHECK-LE-DAG: li 7, 5379; CHECK-LE-DAG: li 8, 6380; CHECK-LE-DAG: li 9, 7381; CHECK-LE-DAG: ld 10, 0([[P7BASEREG:[0-9]+]])382; CHECK-LE-DAG: ld [[TMPREG:[0-9]+]], 8([[P7BASEREG]])383; CHECK-LE-DAG: std [[TMPREG]], [[OFFSET:[0-9]+]](1)384; CHECK-LE: bl callee_i128_split385 386 387; CHECK-BE-LABEL: @i128_split388; CHECK-BE-DAG: li 3, 1389; CHECK-BE-DAG: ld 4, 0([[P2BASEREG:[0-9]+]])390; CHECK-BE-DAG: ld 5, 8([[P2BASEREG]])391; CHECK-BE-DAG: li 6, 4392; CHECK-BE-DAG: li 7, 5393; CHECK-BE-DAG: li 8, 6394; CHECK-BE-DAG: li 9, 7395; CHECK-BE-DAG: ld 10, 0([[P7BASEREG:[0-9]+]])396; CHECK-BE-DAG: ld [[TMPREG:[0-9]+]], 8([[P7BASEREG]])397; CHECK-BE-DAG: std [[TMPREG]], [[OFFSET:[0-9]+]](1)398; CHECK-BE: bl {{.?}}callee_i128_split399 400; CHECK-NOVSX-LABEL: @i128_split401; CHECK-NOVSX-DAG: li 3, 1402; CHECK-NOVSX-DAG: ld 4, 0([[P2BASEREG:[0-9]+]])403; CHECK-NOVSX-DAG: ld 5, 8([[P2BASEREG]])404; CHECK-NOVSX-DAG: li 6, 4405; CHECK-NOVSX-DAG: li 7, 5406; CHECK-NOVSX-DAG: li 8, 6407; CHECK-NOVSX-DAG: li 9, 7408; CHECK-NOVSX-DAG: ld 10, 0([[P7BASEREG:[0-9]+]])409; CHECK-NOVSX-DAG: ld [[TMPREG:[0-9]+]], 8([[P7BASEREG]])410; CHECK-NOVSX-DAG: std [[TMPREG]], [[OFFSET:[0-9]+]](1)411; CHECK-NOVSX: bl {{.?}}callee_i128_split412