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1; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr8 \2; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s3; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mattr=+altivec \4; RUN: -mattr=-vsx | FileCheck %s5; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr9 \6; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s7 8; Currently VSX support is disabled for this test because we generate lxsdx9; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we10; have reg+imm addressing, and is on the list of things to be fixed.11; The second run step is to ensure that is adequate to select12; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le.13 14target datalayout = "e-m:e-i64:64-n32:64"15target triple = "powerpc64le-unknown-linux-gnu"16 17;18; Verify use of registers for float/vector aggregate return.19;20 21define [8 x float] @return_float([8 x float] %x) {22entry:23 ret [8 x float] %x24}25; CHECK-LABEL: @return_float26; CHECK: %entry27; CHECK-NEXT: blr28 29define [8 x double] @return_double([8 x double] %x) {30entry:31 ret [8 x double] %x32}33; CHECK-LABEL: @return_double34; CHECK: %entry35; CHECK-NEXT: blr36 37define [4 x ppc_fp128] @return_ppcf128([4 x ppc_fp128] %x) {38entry:39 ret [4 x ppc_fp128] %x40}41; CHECK-LABEL: @return_ppcf12842; CHECK: %entry43; CHECK-NEXT: blr44 45define [8 x <4 x i32>] @return_v4i32([8 x <4 x i32>] %x) {46entry:47 ret [8 x <4 x i32>] %x48}49; CHECK-LABEL: @return_v4i3250; CHECK: %entry51; CHECK-NEXT: blr52 53 54;55; Verify amount of space taken up by aggregates in the parameter save area.56;57 58define i64 @callee_float([7 x float] %a, [7 x float] %b, i64 %c) {59entry:60 ret i64 %c61}62; CHECK-LABEL: @callee_float63; CHECK: ld 3, 96(1)64; CHECK: blr65 66define void @caller_float(i64 %x, [7 x float] %y) {67entry:68 tail call void @test_float([7 x float] %y, [7 x float] %y, i64 %x)69 ret void70}71; CHECK-LABEL: @caller_float72; CHECK: std 3, 96(1)73; CHECK: bl test_float74 75declare void @test_float([7 x float], [7 x float], i64)76 77define i64 @callee_double(i64 %a, [7 x double] %b, i64 %c) {78entry:79 ret i64 %c80}81; CHECK-LABEL: @callee_double82; CHECK: ld 3, 96(1)83; CHECK: blr84 85define void @caller_double(i64 %x, [7 x double] %y) {86entry:87 tail call void @test_double(i64 %x, [7 x double] %y, i64 %x)88 ret void89}90; CHECK-LABEL: @caller_double91; CHECK: std 3, 96(1)92; CHECK: bl test_double93 94declare void @test_double(i64, [7 x double], i64)95 96define i64 @callee_ppcf128(i64 %a, [4 x ppc_fp128] %b, i64 %c) {97entry:98 ret i64 %c99}100; CHECK-LABEL: @callee_ppcf128101; CHECK: ld 3, 104(1)102; CHECK: blr103 104define void @caller_ppcf128(i64 %x, [4 x ppc_fp128] %y) {105entry:106 tail call void @test_ppcf128(i64 %x, [4 x ppc_fp128] %y, i64 %x)107 ret void108}109; CHECK-LABEL: @caller_ppcf128110; CHECK: std 3, 104(1)111; CHECK: bl test_ppcf128112 113declare void @test_ppcf128(i64, [4 x ppc_fp128], i64)114 115define i64 @callee_i64(i64 %a, [7 x i64] %b, i64 %c) {116entry:117 ret i64 %c118}119; CHECK-LABEL: @callee_i64120; CHECK: ld 3, 96(1)121; CHECK: blr122 123define void @caller_i64(i64 %x, [7 x i64] %y) {124entry:125 tail call void @test_i64(i64 %x, [7 x i64] %y, i64 %x)126 ret void127}128; CHECK-LABEL: @caller_i64129; CHECK: std 3, 96(1)130; CHECK: bl test_i64131 132declare void @test_i64(i64, [7 x i64], i64)133 134define i64 @callee_i128(i64 %a, [4 x i128] %b, i64 %c) {135entry:136 ret i64 %c137}138; CHECK-LABEL: @callee_i128139; CHECK: ld 3, 112(1)140; CHECK: blr141 142define void @caller_i128(i64 %x, [4 x i128] %y) {143entry:144 tail call void @test_i128(i64 %x, [4 x i128] %y, i64 %x)145 ret void146}147; CHECK-LABEL: @caller_i128148; CHECK: std 3, 112(1)149; CHECK: bl test_i128150 151declare void @test_i128(i64, [4 x i128], i64)152 153define i64 @callee_v4i32(i64 %a, [4 x <4 x i32>] %b, i64 %c) {154entry:155 ret i64 %c156}157; CHECK-LABEL: @callee_v4i32158; CHECK: ld 3, 112(1)159; CHECK: blr160 161define void @caller_v4i32(i64 %x, [4 x <4 x i32>] %y) {162entry:163 tail call void @test_v4i32(i64 %x, [4 x <4 x i32>] %y, i64 %x)164 ret void165}166; CHECK-LABEL: @caller_v4i32167; CHECK: std 3, 112(1)168; CHECK: bl test_v4i32169 170declare void @test_v4i32(i64, [4 x <4 x i32>], i64)171 172 173;174; Verify handling of floating point arguments in GPRs175;176 177%struct.float8 = type { [8 x float] }178%struct.float5 = type { [5 x float] }179%struct.float2 = type { [2 x float] }180 181@g8 = common global %struct.float8 zeroinitializer, align 4182@g5 = common global %struct.float5 zeroinitializer, align 4183@g2 = common global %struct.float2 zeroinitializer, align 4184 185define float @callee0([7 x float] %a, [7 x float] %b) {186entry:187 %b.extract = extractvalue [7 x float] %b, 6188 ret float %b.extract189}190; CHECK-LABEL: @callee0191; CHECK: stw 10, [[OFF:.*]](1)192; CHECK: lfs 1, [[OFF]](1)193; CHECK: blr194 195define void @caller0([7 x float] %a) {196entry:197 tail call void @test0([7 x float] %a, [7 x float] %a)198 ret void199}200; CHECK-LABEL: @caller0201; CHECK-DAG: fmr 8, 1202; CHECK-DAG: fmr 9, 2203; CHECK-DAG: fmr 10, 3204; CHECK-DAG: fmr 11, 4205; CHECK-DAG: fmr 12, 5206; CHECK-DAG: fmr 13, 6207; CHECK-DAG: stfs 7, [[OFF:[0-9]+]](1)208; CHECK-DAG: lwz 10, [[OFF]](1)209; CHECK: bl test0210 211declare void @test0([7 x float], [7 x float])212 213define float @callee1([8 x float] %a, [8 x float] %b) {214entry:215 %b.extract = extractvalue [8 x float] %b, 7216 ret float %b.extract217}218; CHECK-LABEL: @callee1219; CHECK: rldicl [[REG:[0-9]+]], 10, 32, 32220; CHECK: stw [[REG]], [[OFF:.*]](1)221; CHECK: lfs 1, [[OFF]](1)222; CHECK: blr223 224define void @caller1([8 x float] %a) {225entry:226 tail call void @test1([8 x float] %a, [8 x float] %a)227 ret void228}229; CHECK-LABEL: @caller1230; CHECK-DAG: fmr 9, 1231; CHECK-DAG: fmr 10, 2232; CHECK-DAG: fmr 11, 3233; CHECK-DAG: fmr 12, 4234; CHECK-DAG: fmr 13, 5235; CHECK-DAG: stfs 5, [[OFF0:[0-9]+]](1)236; CHECK-DAG: stfs 6, [[OFF1:[0-9]+]](1)237; CHECK-DAG: stfs 7, [[OFF2:[0-9]+]](1)238; CHECK-DAG: stfs 8, [[OFF3:[0-9]+]](1)239; CHECK-DAG: lwz 9, [[OFF0]](1)240; CHECK-DAG: lwz [[REG1:[0-9]+]], [[OFF1]](1)241; CHECK-DAG: lwz 10, [[OFF2]](1)242; CHECK-DAG: lwz [[REG3:[0-9]+]], [[OFF3]](1)243; CHECK-DAG: rldimi 9, [[REG1]], 32, 0244; CHECK-DAG: rldimi 10, [[REG3]], 32, 0245; CHECK: bl test1246 247declare void @test1([8 x float], [8 x float])248 249define float @callee2([8 x float] %a, [5 x float] %b, [2 x float] %c) {250entry:251 %c.extract = extractvalue [2 x float] %c, 1252 ret float %c.extract253}254; CHECK-LABEL: @callee2255; CHECK: rldicl [[REG:[0-9]+]], 10, 32, 32256; CHECK: stw [[REG]], [[OFF:.*]](1)257; CHECK: lfs 1, [[OFF]](1)258; CHECK: blr259 260define void @caller2() {261entry:262 %0 = load [8 x float], ptr @g8, align 4263 %1 = load [5 x float], ptr @g5, align 4264 %2 = load [2 x float], ptr @g2, align 4265 tail call void @test2([8 x float] %0, [5 x float] %1, [2 x float] %2)266 ret void267}268; CHECK-LABEL: @caller2269; CHECK: ld {{[0-9]+}}, .LC270; CHECK-DAG: lfs 1, 0({{[0-9]+}})271; CHECK-DAG: lfs 2, 4({{[0-9]+}})272; CHECK-DAG: lfs 3, 8({{[0-9]+}})273; CHECK-DAG: lfs 4, 12({{[0-9]+}})274; CHECK-DAG: lfs 5, 16({{[0-9]+}})275; CHECK-DAG: lfs 6, 20({{[0-9]+}})276; CHECK-DAG: lfs 7, 24({{[0-9]+}})277; CHECK-DAG: lfs 8, 28({{[0-9]+}})278 279; CHECK-DAG: lfs 9, 0({{[0-9]+}})280; CHECK-DAG: lfs 10, 4({{[0-9]+}})281; CHECK-DAG: lfs 11, 8({{[0-9]+}})282; CHECK-DAG: lfs 12, 12({{[0-9]+}})283; CHECK-DAG: lfs 13, 16({{[0-9]+}})284 285; CHECK-DAG: ld 10, 0({{[0-9]+}})286; CHECK: bl test2287 288declare void @test2([8 x float], [5 x float], [2 x float])289 290define double @callee3([8 x float] %a, [5 x float] %b, double %c) {291entry:292 ret double %c293}294; CHECK-LABEL: @callee3295; CHECK: std 10, [[OFF:.*]](1)296; CHECK: lfd 1, [[OFF]](1)297; CHECK: blr298 299define void @caller3(double %d) {300entry:301 %0 = load [8 x float], ptr @g8, align 4302 %1 = load [5 x float], ptr @g5, align 4303 tail call void @test3([8 x float] %0, [5 x float] %1, double %d)304 ret void305}306; CHECK-LABEL: @caller3307; CHECK: stfd 1, [[OFF:.*]](1)308; CHECK: ld 10, [[OFF]](1)309; CHECK: bl test3310 311declare void @test3([8 x float], [5 x float], double)312 313define float @callee4([8 x float] %a, [5 x float] %b, float %c) {314entry:315 ret float %c316}317; CHECK-LABEL: @callee4318; CHECK: stw 10, [[OFF:.*]](1)319; CHECK: lfs 1, [[OFF]](1)320; CHECK: blr321 322define void @caller4(float %f) {323entry:324 %0 = load [8 x float], ptr @g8, align 4325 %1 = load [5 x float], ptr @g5, align 4326 tail call void @test4([8 x float] %0, [5 x float] %1, float %f)327 ret void328}329; CHECK-LABEL: @caller4330; CHECK: stfs 1, [[OFF:.*]](1)331; CHECK: lwz 10, [[OFF]](1)332; CHECK: bl test4333 334declare void @test4([8 x float], [5 x float], float)335 336