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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \3; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names < %s | \4; RUN: FileCheck %s5; Function Attrs: nounwind readnone speculatable6declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #07 8; Function Attrs: nounwind readnone speculatable9declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #010 11define void @draw_llvm_vs_variant0(<4 x float> %x) {12; CHECK-LABEL: draw_llvm_vs_variant0:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: lxsihzx v3, 0, r315; CHECK-NEXT: vextsh2w v3, v316; CHECK-NEXT: xxmrghw v3, v3, v317; CHECK-NEXT: xvcvsxwsp vs0, v318; CHECK-NEXT: xxspltw vs0, vs0, 219; CHECK-NEXT: xvmaddasp vs0, v2, v220; CHECK-NEXT: stxv vs0, 0(r3)21; CHECK-NEXT: blr22entry:23 %.size = load i32, ptr undef24 %0 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %.size, i32 7)25 %1 = extractvalue { i32, i1 } %0, 026 %2 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %1, i32 0)27 %3 = extractvalue { i32, i1 } %2, 028 %4 = select i1 false, i32 0, i32 %329 %5 = xor i1 false, true30 %6 = sext i1 %5 to i3231 %7 = load <4 x i16>, ptr undef, align 232 %8 = extractelement <4 x i16> %7, i32 033 %9 = sext i16 %8 to i3234 %10 = insertelement <4 x i32> undef, i32 %9, i32 035 %11 = extractelement <4 x i16> %7, i32 136 %12 = sext i16 %11 to i3237 %13 = insertelement <4 x i32> %10, i32 %12, i32 138 %14 = extractelement <4 x i16> %7, i32 239 %15 = sext i16 %14 to i3240 %16 = insertelement <4 x i32> %13, i32 %15, i32 241 %17 = extractelement <4 x i16> %7, i32 342 %18 = sext i16 %17 to i3243 %19 = insertelement <4 x i32> %16, i32 %18, i32 344 %20 = sitofp <4 x i32> %19 to <4 x float>45 %21 = insertelement <4 x i32> undef, i32 %6, i32 046 %22 = shufflevector <4 x i32> %21, <4 x i32> undef, <4 x i32> zeroinitializer47 %23 = bitcast <4 x float> %20 to <4 x i32>48 %24 = and <4 x i32> %23, %2249 %25 = bitcast <4 x i32> %24 to <4 x float>50 %26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>51 %27 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %x, <4 x float> %x, <4 x float> %26)52 store <4 x float> %27, ptr undef53 ret void54}55