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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \3; RUN: -mcpu=pwr6 -ppc-asm-full-reg-names -mattr=-vsx \4; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s5 6; There is code in the SDAG to expand FMAX/FMIN with fast flags to SELECT_CC.7; On PPC, we had SELECT_CC legalized using Promote for all vector types8; (including the type that they are all promoted to - which caused an infinite9; loop in legalization). This test just ensures that we terminate on such input.10define dso_local void @_ZN1a1bEv(<4 x float> %in) local_unnamed_addr #0 align 2 {11; CHECK-LABEL: _ZN1a1bEv:12; CHECK: # %bb.0:13; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_414; CHECK-NEXT: b .LBB0_115; CHECK-NEXT: .LBB0_1: # %.preheader16; CHECK-NEXT: b .LBB0_217; CHECK-NEXT: .LBB0_2:18; CHECK-NEXT: b .LBB0_319; CHECK-NEXT: .LBB0_3:20; CHECK-NEXT: .LBB0_4:21; CHECK-NEXT: blr22 br i1 undef, label %7, label %123 241: ; preds = %1, %025 br i1 undef, label %2, label %126 272: ; preds = %128 %3 = shufflevector <4 x float> %in, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>29 %4 = call fast <4 x float> @llvm.maxnum.v4f32(<4 x float> %3, <4 x float> zeroinitializer)30 %5 = call fast <4 x float> @llvm.maxnum.v4f32(<4 x float> %4, <4 x float> undef)31 %6 = extractelement <4 x float> %5, i32 032 br label %733 347: ; preds = %2, %035 %8 = phi float [ %6, %2 ], [ undef, %0 ]36 %9 = fcmp fast une float %8, 0.000000e+0037 ret void38}39 40declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #041 42attributes #0 = { nounwind optnone noinline }43