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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -simplify-mir -verify-machineinstrs < %s | FileCheck %s3 4target datalayout = "e-m:e-i64:64-n32:64"5target triple = "powerpc64le-grtev4-linux-gnu"6 7define void @foo(ptr %p1, i64 %v1, i8 %v2, i64 %v3) {8; CHECK-LABEL: foo:9; CHECK: # %bb.0:10; CHECK-NEXT: li 7, 011; CHECK-NEXT: std 7, 0(3)12; CHECK-NEXT: mr 7, 513; CHECK-NEXT: rldimi. 7, 4, 8, 014; CHECK-NEXT: crnot 20, 215; CHECK-NEXT: andi. 5, 5, 116; CHECK-NEXT: bc 4, 1, .LBB0_217; CHECK-NEXT: # %bb.1: # %bb118; CHECK-NEXT: std 4, 0(3)19; CHECK-NEXT: .LBB0_2: # %bb220; CHECK-NEXT: bclr 12, 20, 021; CHECK-NEXT: # %bb.3: # %bb322; CHECK-NEXT: std 6, 0(3)23; CHECK-NEXT: blr24 store i64 0, ptr %p1, align 825 %ext = zext i8 %v2 to i6426 %shift = shl nuw i64 %v1, 827 %merge = or i64 %shift, %ext28 %not0 = icmp ne i64 %merge, 029 %bit0 = and i64 %ext, 1 ; and & icmp instructions can be combined30 %cond1 = icmp eq i64 %bit0, 0 ; to and. and generates condition code to31 br i1 %cond1, label %bb2, label %bb1 ; be used by this conditional branch32 33bb1:34 store i64 %v1, ptr %p1, align 835 br label %bb236 37bb2:38 br i1 %not0, label %exit, label %bb339 40bb3:41 store i64 %v3, ptr %p1, align 842 br label %exit43 44exit:45 ret void46}47