174 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -disable-ppc-instr-form-prep=true -mcpu=pwr9 < %s \3; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck %s -check-prefix=CHECK-P94; RUN: llc -verify-machineinstrs -disable-ppc-instr-form-prep=true -mcpu=pwr10 < %s \5; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck %s -check-prefix=CHECK-P106 7target triple = "powerpc64le-unknown-linux-gnu"8 9%_elem_type_of_a = type <{ double }>10%_elem_type_of_x = type <{ double }>11%_elem_type_of_y = type <{ double }>12 13define void @test(ptr dereferenceable(4) %.ial, ptr noalias dereferenceable(4) %.m, ptr noalias dereferenceable(4) %.n, ptr %.a, ptr noalias dereferenceable(4) %.lda, ptr noalias %.x, ptr noalias %.y) {14; CHECK-P9-LABEL: test:15; CHECK-P9: # %bb.0: # %test_entry16; CHECK-P9-NEXT: andi. r3, r6, 1517; CHECK-P9-NEXT: li r3, 218; CHECK-P9-NEXT: li r10, 119; CHECK-P9-NEXT: lwz r4, 0(r4)20; CHECK-P9-NEXT: lwz r5, 0(r5)21; CHECK-P9-NEXT: iseleq r3, r10, r322; CHECK-P9-NEXT: subfic r10, r3, 123; CHECK-P9-NEXT: add r4, r10, r424; CHECK-P9-NEXT: srawi r4, r4, 425; CHECK-P9-NEXT: addze r4, r426; CHECK-P9-NEXT: srawi r5, r5, 127; CHECK-P9-NEXT: slwi r4, r4, 428; CHECK-P9-NEXT: addze r5, r529; CHECK-P9-NEXT: sub r4, r4, r1030; CHECK-P9-NEXT: cmpw r3, r431; CHECK-P9-NEXT: bgtlr cr032; CHECK-P9-NEXT: # %bb.1: # %_loop_2_do_.lr.ph33; CHECK-P9-NEXT: extswsli r5, r5, 334; CHECK-P9-NEXT: add r5, r8, r535; CHECK-P9-NEXT: addi r8, r5, -836; CHECK-P9-NEXT: lwz r5, 0(r7)37; CHECK-P9-NEXT: extsw r7, r438; CHECK-P9-NEXT: rldic r4, r3, 3, 2939; CHECK-P9-NEXT: sub r3, r7, r340; CHECK-P9-NEXT: addi r10, r4, 841; CHECK-P9-NEXT: lxvdsx vs0, 0, r842; CHECK-P9-NEXT: rldicl r3, r3, 60, 443; CHECK-P9-NEXT: extswsli r5, r5, 344; CHECK-P9-NEXT: addi r3, r3, 145; CHECK-P9-NEXT: sub r4, r10, r546; CHECK-P9-NEXT: add r5, r9, r1047; CHECK-P9-NEXT: mtctr r348; CHECK-P9-NEXT: add r4, r6, r449; CHECK-P9-NEXT: .p2align 450; CHECK-P9-NEXT: .LBB0_2: # %_loop_2_do_51; CHECK-P9-NEXT: #52; CHECK-P9-NEXT: lxv vs1, -16(r5)53; CHECK-P9-NEXT: lxv vs2, 0(r5)54; CHECK-P9-NEXT: lxv vs3, -16(r4)55; CHECK-P9-NEXT: lxv vs4, 0(r4)56; CHECK-P9-NEXT: addi r4, r4, 12857; CHECK-P9-NEXT: xvmaddadp vs1, vs3, vs158; CHECK-P9-NEXT: stxv vs1, -16(r5)59; CHECK-P9-NEXT: xvmaddadp vs2, vs4, vs060; CHECK-P9-NEXT: stxv vs2, 0(r5)61; CHECK-P9-NEXT: addi r5, r5, 12862; CHECK-P9-NEXT: bdnz .LBB0_263; CHECK-P9-NEXT: # %bb.3: # %_return_bb64; CHECK-P9-NEXT: blr65;66; CHECK-P10-LABEL: test:67; CHECK-P10: # %bb.0: # %test_entry68; CHECK-P10-NEXT: andi. r3, r6, 1569; CHECK-P10-NEXT: li r3, 270; CHECK-P10-NEXT: li r10, 171; CHECK-P10-NEXT: lwz r4, 0(r4)72; CHECK-P10-NEXT: lwz r5, 0(r5)73; CHECK-P10-NEXT: iseleq r3, r10, r374; CHECK-P10-NEXT: subfic r10, r3, 175; CHECK-P10-NEXT: add r4, r10, r476; CHECK-P10-NEXT: srawi r4, r4, 477; CHECK-P10-NEXT: addze r4, r478; CHECK-P10-NEXT: srawi r5, r5, 179; CHECK-P10-NEXT: slwi r4, r4, 480; CHECK-P10-NEXT: addze r5, r581; CHECK-P10-NEXT: sub r4, r4, r1082; CHECK-P10-NEXT: cmpw r3, r483; CHECK-P10-NEXT: bgtlr cr084; CHECK-P10-NEXT: # %bb.1: # %_loop_2_do_.lr.ph85; CHECK-P10-NEXT: extswsli r5, r5, 386; CHECK-P10-NEXT: add r5, r8, r587; CHECK-P10-NEXT: addi r8, r5, -888; CHECK-P10-NEXT: lwz r5, 0(r7)89; CHECK-P10-NEXT: extsw r7, r490; CHECK-P10-NEXT: rldic r4, r3, 3, 2991; CHECK-P10-NEXT: addi r10, r4, 892; CHECK-P10-NEXT: sub r3, r7, r393; CHECK-P10-NEXT: lxvdsx vs0, 0, r894; CHECK-P10-NEXT: rldicl r3, r3, 60, 495; CHECK-P10-NEXT: extswsli r5, r5, 396; CHECK-P10-NEXT: addi r3, r3, 197; CHECK-P10-NEXT: sub r4, r10, r598; CHECK-P10-NEXT: add r5, r9, r1099; CHECK-P10-NEXT: mtctr r3100; CHECK-P10-NEXT: add r4, r6, r4101; CHECK-P10-NEXT: .p2align 4102; CHECK-P10-NEXT: .LBB0_2: # %_loop_2_do_103; CHECK-P10-NEXT: #104; CHECK-P10-NEXT: lxv vs1, -16(r5)105; CHECK-P10-NEXT: lxv vs2, 0(r5)106; CHECK-P10-NEXT: lxv vs3, -16(r4)107; CHECK-P10-NEXT: xvmaddadp vs1, vs3, vs1108; CHECK-P10-NEXT: lxv vs4, 0(r4)109; CHECK-P10-NEXT: xvmaddadp vs2, vs4, vs0110; CHECK-P10-NEXT: addi r4, r4, 128111; CHECK-P10-NEXT: stxv vs1, -16(r5)112; CHECK-P10-NEXT: stxv vs2, 0(r5)113; CHECK-P10-NEXT: addi r5, r5, 128114; CHECK-P10-NEXT: bdnz .LBB0_2115; CHECK-P10-NEXT: # %bb.3: # %_return_bb116; CHECK-P10-NEXT: blr117; FIXME: use pair load/store instructions lxvp/stxvp118test_entry:119 %_conv5 = ptrtoint ptr %.a to i64120 %_andi_tmp = and i64 %_conv5, 15121 %_equ_tmp = icmp eq i64 %_andi_tmp, 0122 %. = select i1 %_equ_tmp, i32 1, i32 2123 %_val_m_ = load i32, ptr %.m, align 4124 %_sub_tmp9 = sub nsw i32 1, %.125 %_add_tmp10 = add i32 %_sub_tmp9, %_val_m_126 %_mod_tmp = srem i32 %_add_tmp10, 16127 %_sub_tmp11 = sub i32 %_val_m_, %_mod_tmp128 %_val_n_ = load i32, ptr %.n, align 4129 %x_rvo_based_addr_17 = getelementptr inbounds [0 x %_elem_type_of_x], ptr %.x, i64 0, i64 -1130 %_div_tmp = sdiv i32 %_val_n_, 2131 %_conv16 = sext i32 %_div_tmp to i64132 %_ind_cast = getelementptr inbounds %_elem_type_of_x, ptr %x_rvo_based_addr_17, i64 %_conv16, i32 0133 %_val_x_ = load double, ptr %_ind_cast, align 8134 %.splatinsert = insertelement <2 x double> undef, double %_val_x_, i32 0135 %.splat = shufflevector <2 x double> %.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer136 %_grt_tmp21 = icmp sgt i32 %., %_sub_tmp11137 br i1 %_grt_tmp21, label %_return_bb, label %_loop_2_do_.lr.ph138 139_loop_2_do_.lr.ph: ; preds = %test_entry140 %_val_lda_ = load i32, ptr %.lda, align 4141 %_conv = sext i32 %_val_lda_ to i64142 %_mult_tmp = shl nsw i64 %_conv, 3143 %_sub_tmp4 = sub nuw nsw i64 -8, %_mult_tmp144 %y_rvo_based_addr_19 = getelementptr inbounds [0 x %_elem_type_of_y], ptr %.y, i64 0, i64 -1145 %a_rvo_based_addr_ = getelementptr inbounds i8, ptr %.a, i64 %_sub_tmp4146 %0 = zext i32 %. to i64147 %1 = sext i32 %_sub_tmp11 to i64148 br label %_loop_2_do_149 150_loop_2_do_: ; preds = %_loop_2_do_.lr.ph, %_loop_2_do_151 %indvars.iv = phi i64 [ %0, %_loop_2_do_.lr.ph ], [ %indvars.iv.next, %_loop_2_do_ ]152 %_ix_x_len19 = shl nuw nsw i64 %indvars.iv, 3153 %y_ix_dim_0_20 = getelementptr inbounds %_elem_type_of_y, ptr %y_rvo_based_addr_19, i64 %indvars.iv154 %2 = load <2 x double>, ptr %y_ix_dim_0_20, align 1155 %3 = getelementptr %_elem_type_of_y, ptr %y_ix_dim_0_20, i64 2156 %4 = load <2 x double>, ptr %3, align 1157 %a_ix_dim_1_ = getelementptr inbounds i8, ptr %a_rvo_based_addr_, i64 %_ix_x_len19158 %5 = load <2 x double>, ptr %a_ix_dim_1_, align 1159 %6 = getelementptr i8, ptr %a_ix_dim_1_, i64 16160 %7 = load <2 x double>, ptr %6, align 1161 %8 = tail call nsz contract <2 x double> @llvm.fma.v2f64(<2 x double> %5, <2 x double> %2, <2 x double> %2)162 %9 = tail call nsz contract <2 x double> @llvm.fma.v2f64(<2 x double> %7, <2 x double> %.splat, <2 x double> %4)163 store <2 x double> %8, ptr %y_ix_dim_0_20, align 1164 store <2 x double> %9, ptr %3, align 1165 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 16166 %_grt_tmp = icmp sgt i64 %indvars.iv.next, %1167 br i1 %_grt_tmp, label %_return_bb, label %_loop_2_do_168 169_return_bb: ; preds = %_loop_2_do_, %test_entry170 ret void171}172 173declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)174