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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \3; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names \4; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names \7; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE8 9; Test reduce scalarization in fpext v2f32 to v2f64 from the extract_subvector v4f32 node.10 11define dso_local void @test(ptr nocapture readonly %a, ptr nocapture %b, ptr nocapture %c) {12; CHECK-LABEL: test:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: lxv vs0, 0(r3)15; CHECK-NEXT: xxmrglw vs1, vs0, vs016; CHECK-NEXT: xxmrghw vs0, vs0, vs017; CHECK-NEXT: xvcvspdp vs1, vs118; CHECK-NEXT: xvcvspdp vs0, vs019; CHECK-NEXT: stxv vs1, 0(r4)20; CHECK-NEXT: stxv vs0, 0(r5)21; CHECK-NEXT: blr22;23; CHECK-BE-LABEL: test:24; CHECK-BE: # %bb.0: # %entry25; CHECK-BE-NEXT: lxv vs0, 0(r3)26; CHECK-BE-NEXT: xxmrghw vs1, vs0, vs027; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs028; CHECK-BE-NEXT: xvcvspdp vs1, vs129; CHECK-BE-NEXT: xvcvspdp vs0, vs030; CHECK-BE-NEXT: stxv vs1, 0(r4)31; CHECK-BE-NEXT: stxv vs0, 0(r5)32; CHECK-BE-NEXT: blr33entry:34 %0 = load <4 x float>, ptr %a, align 1635 %shuffle = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 0, i32 1>36 %shuffle1 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 2, i32 3>37 %vecinit4 = fpext <2 x float> %shuffle to <2 x double>38 %vecinit11 = fpext <2 x float> %shuffle1 to <2 x double>39 store <2 x double> %vecinit4, ptr %b, align 1640 store <2 x double> %vecinit11, ptr %c, align 1641 ret void42}43 44; Ensure we don't crash for wider types45 46define dso_local void @test2(ptr nocapture readonly %a, ptr nocapture %b, ptr nocapture %c) {47; CHECK-LABEL: test2:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: lxv vs0, 0(r3)50; CHECK-NEXT: xxmrglw vs1, vs0, vs051; CHECK-NEXT: xxmrghw vs0, vs0, vs052; CHECK-NEXT: xvcvspdp vs1, vs153; CHECK-NEXT: xvcvspdp vs0, vs054; CHECK-NEXT: stxv vs1, 0(r4)55; CHECK-NEXT: stxv vs0, 0(r5)56; CHECK-NEXT: blr57;58; CHECK-BE-LABEL: test2:59; CHECK-BE: # %bb.0: # %entry60; CHECK-BE-NEXT: lxv vs0, 0(r3)61; CHECK-BE-NEXT: xxmrghw vs1, vs0, vs062; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs063; CHECK-BE-NEXT: xvcvspdp vs1, vs164; CHECK-BE-NEXT: xvcvspdp vs0, vs065; CHECK-BE-NEXT: stxv vs1, 0(r4)66; CHECK-BE-NEXT: stxv vs0, 0(r5)67; CHECK-BE-NEXT: blr68entry:69 %0 = load <16 x float>, ptr %a, align 1670 %shuffle = shufflevector <16 x float> %0, <16 x float> undef, <2 x i32> <i32 0, i32 1>71 %shuffle1 = shufflevector <16 x float> %0, <16 x float> undef, <2 x i32> <i32 2, i32 3>72 %vecinit4 = fpext <2 x float> %shuffle to <2 x double>73 %vecinit11 = fpext <2 x float> %shuffle1 to <2 x double>74 store <2 x double> %vecinit4, ptr %b, align 1675 store <2 x double> %vecinit11, ptr %c, align 1676 ret void77}78