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1# RUN: llc -mtriple=powerpc64le-unknown-unknown -start-before ppc-pre-emit-peephole \2# RUN: -verify-machineinstrs -ppc-asm-full-reg-names %s -o - | FileCheck %s3--- |4 ; ModuleID = 't.ll'5 source_filename = "t.ll"6 target datalayout = "e-m:e-i64:64-n32:64"7 8 define signext i32 @test(i32 signext %a, i32 signext %b, i32 signext %c) {9 entry:10 %cmp = icmp slt i32 %a, %b11 br i1 %cmp, label %return, label %if.end12 13 if.end: ; preds = %entry14 %cmp1 = icmp slt i32 %b, %a15 br i1 %cmp1, label %return, label %if.end316 17 if.end3: ; preds = %if.end18 %cmp4 = icmp eq i32 %a, %c19 br i1 %cmp4, label %if.then5, label %if.end620 21 if.then5: ; preds = %if.end322 %add = shl nsw i32 %a, 123 br label %return24 25 if.end6: ; preds = %if.end326 %cmp7 = icmp sgt i32 %c, %b27 %add11 = add i32 %c, %b28 %add12 = select i1 %cmp7, i32 %a, i32 029 %spec.select = add i32 %add11, %add1230 ret i32 %spec.select31 32 return: ; preds = %if.then5, %if.end, %entry33 %retval.0 = phi i32 [ %add, %if.then5 ], [ %c, %entry ], [ %b, %if.end ]34 ret i32 %retval.035 }36 37...38---39name: test40alignment: 1641exposesReturnsTwice: false42legalized: false43regBankSelected: false44selected: false45failedISel: false46tracksRegLiveness: true47registers: 48liveins: 49 - { reg: '$x3', virtual-reg: '' }50 - { reg: '$x4', virtual-reg: '' }51 - { reg: '$x5', virtual-reg: '' }52frameInfo: 53 isFrameAddressTaken: false54 isReturnAddressTaken: false55 hasStackMap: false56 hasPatchPoint: false57 stackSize: 058 offsetAdjustment: 059 maxAlignment: 060 adjustsStack: false61 hasCalls: false62 stackProtector: ''63 maxCallFrameSize: 064 hasOpaqueSPAdjustment: false65 hasVAStart: false66 hasMustTailInVarArgFunc: false67 localFrameSize: 068 savePoint: []69 restorePoint: []70fixedStack: 71stack: 72constants: 73body: |74 bb.0.entry:75 successors: %bb.4(0x40000000), %bb.1(0x40000000)76 liveins: $x3, $x4, $x577 78 renamable $cr0 = CMPW renamable $r3, renamable $r479 BCC 12, renamable $cr0, %bb.480 81 bb.1.if.end:82 successors: %bb.6(0x40000000), %bb.2(0x40000000)83 liveins: $cr0, $x3, $x4, $x584 85 BCC 36, killed renamable $cr0, %bb.286 87 bb.6:88 liveins: $x489 90 ; CHECK: mr r5, r491 ; CHECK-NOT: mr r5, r592 ; CHECK: extsw r3, r593 $r5 = OR killed $r4, $r4, implicit $x4, implicit-def $x594 $r5 = OR $r5, $r5, implicit-def $x595 renamable $x3 = EXTSW_32_64 killed renamable $r5, implicit $x596 BLR8 implicit $lr8, implicit $rm, implicit killed $x397 98 bb.2.if.end3:99 successors: %bb.3(0x40000000), %bb.5(0x40000000)100 liveins: $x3, $x4, $x5101 102 renamable $cr0 = CMPLW renamable $r3, renamable $r5103 BCC 68, killed renamable $cr0, %bb.5104 105 bb.3.if.then5:106 successors: %bb.4(0x80000000)107 liveins: $x3108 109 renamable $r5 = RLWINM killed renamable $r3, 1, 0, 30, implicit $x3, implicit-def $x5110 111 bb.4.return:112 liveins: $x5113 114 renamable $x3 = EXTSW_32_64 killed renamable $r5, implicit $x5115 BLR8 implicit $lr8, implicit $rm, implicit killed $x3116 117 bb.5.if.end6:118 liveins: $x3, $x4, $x5119 120 renamable $cr0 = CMPW renamable $r5, renamable $r4121 renamable $r6 = LI 0122 renamable $r4 = ADD4 killed renamable $r5, killed renamable $r4, implicit $x4, implicit $x5123 renamable $r3 = ISEL killed renamable $r3, killed renamable $r6, killed renamable $cr0gt, implicit $cr0, implicit $x3124 renamable $r3 = ADD4 killed renamable $r4, killed renamable $r3125 renamable $x3 = EXTSW_32_64 killed renamable $r3126 BLR8 implicit $lr8, implicit $rm, implicit killed $x3127 128...129