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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s3 4; There are at least 3 potential patterns corresponding to an unsigned saturated add: min, cmp with sum, cmp with not.5; Test each of those patterns with i8/i16/i32/i64.6; Test each of those with a constant operand and a variable operand.7; Test each of those with a 128-bit vector type.8 9define i8 @unsigned_sat_constant_i8_using_min(i8 %x) {10; CHECK-LABEL: unsigned_sat_constant_i8_using_min:11; CHECK: # %bb.0:12; CHECK-NEXT: clrlwi 4, 3, 2413; CHECK-NEXT: cmplwi 4, 21314; CHECK-NEXT: li 4, -4315; CHECK-NEXT: isellt 3, 3, 416; CHECK-NEXT: addi 3, 3, 4217; CHECK-NEXT: blr18 %c = icmp ult i8 %x, -4319 %s = select i1 %c, i8 %x, i8 -4320 %r = add i8 %s, 4221 ret i8 %r22}23 24define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {25; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:26; CHECK: # %bb.0:27; CHECK-NEXT: clrlwi 3, 3, 2428; CHECK-NEXT: addi 3, 3, 4229; CHECK-NEXT: andi. 4, 3, 25630; CHECK-NEXT: li 4, -131; CHECK-NEXT: iseleq 3, 3, 432; CHECK-NEXT: blr33 %a = add i8 %x, 4234 %c = icmp ugt i8 %x, %a35 %r = select i1 %c, i8 -1, i8 %a36 ret i8 %r37}38 39define i8 @unsigned_sat_constant_i8_using_cmp_notval(i8 %x) {40; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_notval:41; CHECK: # %bb.0:42; CHECK-NEXT: clrlwi 4, 3, 2443; CHECK-NEXT: addi 3, 3, 4244; CHECK-NEXT: cmplwi 4, 21345; CHECK-NEXT: li 4, -146; CHECK-NEXT: iselgt 3, 4, 347; CHECK-NEXT: blr48 %a = add i8 %x, 4249 %c = icmp ugt i8 %x, -4350 %r = select i1 %c, i8 -1, i8 %a51 ret i8 %r52}53 54define i16 @unsigned_sat_constant_i16_using_min(i16 %x) {55; CHECK-LABEL: unsigned_sat_constant_i16_using_min:56; CHECK: # %bb.0:57; CHECK-NEXT: clrlwi 4, 3, 1658; CHECK-NEXT: cmplwi 4, 6549359; CHECK-NEXT: li 4, -4360; CHECK-NEXT: isellt 3, 3, 461; CHECK-NEXT: addi 3, 3, 4262; CHECK-NEXT: blr63 %c = icmp ult i16 %x, -4364 %s = select i1 %c, i16 %x, i16 -4365 %r = add i16 %s, 4266 ret i16 %r67}68 69define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {70; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:71; CHECK: # %bb.0:72; CHECK-NEXT: clrlwi 3, 3, 1673; CHECK-NEXT: addi 3, 3, 4274; CHECK-NEXT: andis. 4, 3, 175; CHECK-NEXT: li 4, -176; CHECK-NEXT: iseleq 3, 3, 477; CHECK-NEXT: blr78 %a = add i16 %x, 4279 %c = icmp ugt i16 %x, %a80 %r = select i1 %c, i16 -1, i16 %a81 ret i16 %r82}83 84define i16 @unsigned_sat_constant_i16_using_cmp_notval(i16 %x) {85; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_notval:86; CHECK: # %bb.0:87; CHECK-NEXT: clrlwi 4, 3, 1688; CHECK-NEXT: addi 3, 3, 4289; CHECK-NEXT: cmplwi 4, 6549390; CHECK-NEXT: li 4, -191; CHECK-NEXT: iselgt 3, 4, 392; CHECK-NEXT: blr93 %a = add i16 %x, 4294 %c = icmp ugt i16 %x, -4395 %r = select i1 %c, i16 -1, i16 %a96 ret i16 %r97}98 99define i32 @unsigned_sat_constant_i32_using_min(i32 %x) {100; CHECK-LABEL: unsigned_sat_constant_i32_using_min:101; CHECK: # %bb.0:102; CHECK-NEXT: li 4, -43103; CHECK-NEXT: cmplw 3, 4104; CHECK-NEXT: isellt 3, 3, 4105; CHECK-NEXT: addi 3, 3, 42106; CHECK-NEXT: blr107 %c = icmp ult i32 %x, -43108 %s = select i1 %c, i32 %x, i32 -43109 %r = add i32 %s, 42110 ret i32 %r111}112 113define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) {114; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_sum:115; CHECK: # %bb.0:116; CHECK-NEXT: addi 4, 3, 42117; CHECK-NEXT: cmplw 4, 3118; CHECK-NEXT: li 3, -1119; CHECK-NEXT: isellt 3, 3, 4120; CHECK-NEXT: blr121 %a = add i32 %x, 42122 %c = icmp ugt i32 %x, %a123 %r = select i1 %c, i32 -1, i32 %a124 ret i32 %r125}126 127define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) {128; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_notval:129; CHECK: # %bb.0:130; CHECK-NEXT: li 5, -43131; CHECK-NEXT: addi 4, 3, 42132; CHECK-NEXT: cmplw 3, 5133; CHECK-NEXT: li 3, -1134; CHECK-NEXT: iselgt 3, 3, 4135; CHECK-NEXT: blr136 %a = add i32 %x, 42137 %c = icmp ugt i32 %x, -43138 %r = select i1 %c, i32 -1, i32 %a139 ret i32 %r140}141 142define i64 @unsigned_sat_constant_i64_using_min(i64 %x) {143; CHECK-LABEL: unsigned_sat_constant_i64_using_min:144; CHECK: # %bb.0:145; CHECK-NEXT: li 4, -43146; CHECK-NEXT: cmpld 3, 4147; CHECK-NEXT: isellt 3, 3, 4148; CHECK-NEXT: addi 3, 3, 42149; CHECK-NEXT: blr150 %c = icmp ult i64 %x, -43151 %s = select i1 %c, i64 %x, i64 -43152 %r = add i64 %s, 42153 ret i64 %r154}155 156define i64 @unsigned_sat_constant_i64_using_cmp_sum(i64 %x) {157; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_sum:158; CHECK: # %bb.0:159; CHECK-NEXT: li 4, 0160; CHECK-NEXT: addic 3, 3, 42161; CHECK-NEXT: addze. 4, 4162; CHECK-NEXT: li 4, -1163; CHECK-NEXT: iseleq 3, 3, 4164; CHECK-NEXT: blr165 %a = add i64 %x, 42166 %c = icmp ugt i64 %x, %a167 %r = select i1 %c, i64 -1, i64 %a168 ret i64 %r169}170 171define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) {172; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_notval:173; CHECK: # %bb.0:174; CHECK-NEXT: li 4, 0175; CHECK-NEXT: addic 3, 3, 42176; CHECK-NEXT: addze. 4, 4177; CHECK-NEXT: li 4, -1178; CHECK-NEXT: iseleq 3, 3, 4179; CHECK-NEXT: blr180 %a = add i64 %x, 42181 %c = icmp ugt i64 %x, -43182 %r = select i1 %c, i64 -1, i64 %a183 ret i64 %r184}185 186define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {187; CHECK-LABEL: unsigned_sat_variable_i8_using_min:188; CHECK: # %bb.0:189; CHECK-NEXT: not 6, 4190; CHECK-NEXT: clrlwi 5, 3, 24191; CHECK-NEXT: clrlwi 7, 6, 24192; CHECK-NEXT: cmplw 5, 7193; CHECK-NEXT: isellt 3, 3, 6194; CHECK-NEXT: add 3, 3, 4195; CHECK-NEXT: blr196 %noty = xor i8 %y, -1197 %c = icmp ult i8 %x, %noty198 %s = select i1 %c, i8 %x, i8 %noty199 %r = add i8 %s, %y200 ret i8 %r201}202 203define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {204; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum:205; CHECK: # %bb.0:206; CHECK-NEXT: clrlwi 4, 4, 24207; CHECK-NEXT: clrlwi 3, 3, 24208; CHECK-NEXT: add 3, 3, 4209; CHECK-NEXT: andi. 4, 3, 256210; CHECK-NEXT: li 4, -1211; CHECK-NEXT: iseleq 3, 3, 4212; CHECK-NEXT: blr213 %a = add i8 %x, %y214 %c = icmp ugt i8 %x, %a215 %r = select i1 %c, i8 -1, i8 %a216 ret i8 %r217}218 219define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {220; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_notval:221; CHECK: # %bb.0:222; CHECK-NEXT: not 6, 4223; CHECK-NEXT: clrlwi 5, 3, 24224; CHECK-NEXT: add 3, 3, 4225; CHECK-NEXT: li 4, -1226; CHECK-NEXT: clrlwi 6, 6, 24227; CHECK-NEXT: cmplw 5, 6228; CHECK-NEXT: iselgt 3, 4, 3229; CHECK-NEXT: blr230 %noty = xor i8 %y, -1231 %a = add i8 %x, %y232 %c = icmp ugt i8 %x, %noty233 %r = select i1 %c, i8 -1, i8 %a234 ret i8 %r235}236 237define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) {238; CHECK-LABEL: unsigned_sat_variable_i16_using_min:239; CHECK: # %bb.0:240; CHECK-NEXT: not 6, 4241; CHECK-NEXT: clrlwi 5, 3, 16242; CHECK-NEXT: clrlwi 7, 6, 16243; CHECK-NEXT: cmplw 5, 7244; CHECK-NEXT: isellt 3, 3, 6245; CHECK-NEXT: add 3, 3, 4246; CHECK-NEXT: blr247 %noty = xor i16 %y, -1248 %c = icmp ult i16 %x, %noty249 %s = select i1 %c, i16 %x, i16 %noty250 %r = add i16 %s, %y251 ret i16 %r252}253 254define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {255; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum:256; CHECK: # %bb.0:257; CHECK-NEXT: clrlwi 4, 4, 16258; CHECK-NEXT: clrlwi 3, 3, 16259; CHECK-NEXT: add 3, 3, 4260; CHECK-NEXT: andis. 4, 3, 1261; CHECK-NEXT: li 4, -1262; CHECK-NEXT: iseleq 3, 3, 4263; CHECK-NEXT: blr264 %a = add i16 %x, %y265 %c = icmp ugt i16 %x, %a266 %r = select i1 %c, i16 -1, i16 %a267 ret i16 %r268}269 270define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) {271; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_notval:272; CHECK: # %bb.0:273; CHECK-NEXT: not 6, 4274; CHECK-NEXT: clrlwi 5, 3, 16275; CHECK-NEXT: add 3, 3, 4276; CHECK-NEXT: li 4, -1277; CHECK-NEXT: clrlwi 6, 6, 16278; CHECK-NEXT: cmplw 5, 6279; CHECK-NEXT: iselgt 3, 4, 3280; CHECK-NEXT: blr281 %noty = xor i16 %y, -1282 %a = add i16 %x, %y283 %c = icmp ugt i16 %x, %noty284 %r = select i1 %c, i16 -1, i16 %a285 ret i16 %r286}287 288define i32 @unsigned_sat_variable_i32_using_min(i32 %x, i32 %y) {289; CHECK-LABEL: unsigned_sat_variable_i32_using_min:290; CHECK: # %bb.0:291; CHECK-NEXT: not 5, 4292; CHECK-NEXT: cmplw 3, 5293; CHECK-NEXT: isellt 3, 3, 5294; CHECK-NEXT: add 3, 3, 4295; CHECK-NEXT: blr296 %noty = xor i32 %y, -1297 %c = icmp ult i32 %x, %noty298 %s = select i1 %c, i32 %x, i32 %noty299 %r = add i32 %s, %y300 ret i32 %r301}302 303define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) {304; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_sum:305; CHECK: # %bb.0:306; CHECK-NEXT: add 4, 3, 4307; CHECK-NEXT: cmplw 4, 3308; CHECK-NEXT: li 3, -1309; CHECK-NEXT: isellt 3, 3, 4310; CHECK-NEXT: blr311 %a = add i32 %x, %y312 %c = icmp ugt i32 %x, %a313 %r = select i1 %c, i32 -1, i32 %a314 ret i32 %r315}316 317define i32 @unsigned_sat_variable_i32_using_cmp_notval(i32 %x, i32 %y) {318; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_notval:319; CHECK: # %bb.0:320; CHECK-NEXT: not 5, 4321; CHECK-NEXT: add 4, 3, 4322; CHECK-NEXT: cmplw 3, 5323; CHECK-NEXT: li 3, -1324; CHECK-NEXT: iselgt 3, 3, 4325; CHECK-NEXT: blr326 %noty = xor i32 %y, -1327 %a = add i32 %x, %y328 %c = icmp ugt i32 %x, %noty329 %r = select i1 %c, i32 -1, i32 %a330 ret i32 %r331}332 333define i64 @unsigned_sat_variable_i64_using_min(i64 %x, i64 %y) {334; CHECK-LABEL: unsigned_sat_variable_i64_using_min:335; CHECK: # %bb.0:336; CHECK-NEXT: not 5, 4337; CHECK-NEXT: cmpld 3, 5338; CHECK-NEXT: isellt 3, 3, 5339; CHECK-NEXT: add 3, 3, 4340; CHECK-NEXT: blr341 %noty = xor i64 %y, -1342 %c = icmp ult i64 %x, %noty343 %s = select i1 %c, i64 %x, i64 %noty344 %r = add i64 %s, %y345 ret i64 %r346}347 348define i64 @unsigned_sat_variable_i64_using_cmp_sum(i64 %x, i64 %y) {349; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_sum:350; CHECK: # %bb.0:351; CHECK-NEXT: addc 3, 3, 4352; CHECK-NEXT: li 4, 0353; CHECK-NEXT: addze. 4, 4354; CHECK-NEXT: li 4, -1355; CHECK-NEXT: iseleq 3, 3, 4356; CHECK-NEXT: blr357 %a = add i64 %x, %y358 %c = icmp ugt i64 %x, %a359 %r = select i1 %c, i64 -1, i64 %a360 ret i64 %r361}362 363define i64 @unsigned_sat_variable_i64_using_cmp_notval(i64 %x, i64 %y) {364; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_notval:365; CHECK: # %bb.0:366; CHECK-NEXT: not 5, 4367; CHECK-NEXT: add 4, 3, 4368; CHECK-NEXT: cmpld 3, 5369; CHECK-NEXT: li 3, -1370; CHECK-NEXT: iselgt 3, 3, 4371; CHECK-NEXT: blr372 %noty = xor i64 %y, -1373 %a = add i64 %x, %y374 %c = icmp ugt i64 %x, %noty375 %r = select i1 %c, i64 -1, i64 %a376 ret i64 %r377}378 379define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {380; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min:381; CHECK: # %bb.0:382; CHECK-NEXT: addis 3, 2, .LCPI24_0@toc@ha383; CHECK-NEXT: addi 3, 3, .LCPI24_0@toc@l384; CHECK-NEXT: lxvd2x 35, 0, 3385; CHECK-NEXT: addis 3, 2, .LCPI24_1@toc@ha386; CHECK-NEXT: addi 3, 3, .LCPI24_1@toc@l387; CHECK-NEXT: vminub 2, 2, 3388; CHECK-NEXT: lxvd2x 35, 0, 3389; CHECK-NEXT: vaddubm 2, 2, 3390; CHECK-NEXT: blr391 %c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>392 %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>393 %r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>394 ret <16 x i8> %r395}396 397define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {398; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:399; CHECK: # %bb.0:400; CHECK-NEXT: addis 3, 2, .LCPI25_0@toc@ha401; CHECK-NEXT: addi 3, 3, .LCPI25_0@toc@l402; CHECK-NEXT: lxvd2x 35, 0, 3403; CHECK-NEXT: vaddubs 2, 2, 3404; CHECK-NEXT: blr405 %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>406 %c = icmp ugt <16 x i8> %x, %a407 %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a408 ret <16 x i8> %r409}410 411define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {412; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:413; CHECK: # %bb.0:414; CHECK-NEXT: addis 3, 2, .LCPI26_0@toc@ha415; CHECK-NEXT: addi 3, 3, .LCPI26_0@toc@l416; CHECK-NEXT: lxvd2x 35, 0, 3417; CHECK-NEXT: vaddubs 2, 2, 3418; CHECK-NEXT: blr419 %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>420 %c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>421 %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a422 ret <16 x i8> %r423}424 425define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {426; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min:427; CHECK: # %bb.0:428; CHECK-NEXT: addis 3, 2, .LCPI27_0@toc@ha429; CHECK-NEXT: addi 3, 3, .LCPI27_0@toc@l430; CHECK-NEXT: lxvd2x 35, 0, 3431; CHECK-NEXT: addis 3, 2, .LCPI27_1@toc@ha432; CHECK-NEXT: addi 3, 3, .LCPI27_1@toc@l433; CHECK-NEXT: vminuh 2, 2, 3434; CHECK-NEXT: lxvd2x 35, 0, 3435; CHECK-NEXT: vadduhm 2, 2, 3436; CHECK-NEXT: blr437 %c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>438 %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>439 %r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>440 ret <8 x i16> %r441}442 443define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {444; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:445; CHECK: # %bb.0:446; CHECK-NEXT: addis 3, 2, .LCPI28_0@toc@ha447; CHECK-NEXT: addi 3, 3, .LCPI28_0@toc@l448; CHECK-NEXT: lxvd2x 35, 0, 3449; CHECK-NEXT: vadduhs 2, 2, 3450; CHECK-NEXT: blr451 %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>452 %c = icmp ugt <8 x i16> %x, %a453 %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a454 ret <8 x i16> %r455}456 457define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {458; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:459; CHECK: # %bb.0:460; CHECK-NEXT: addis 3, 2, .LCPI29_0@toc@ha461; CHECK-NEXT: addi 3, 3, .LCPI29_0@toc@l462; CHECK-NEXT: lxvd2x 35, 0, 3463; CHECK-NEXT: vadduhs 2, 2, 3464; CHECK-NEXT: blr465 %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>466 %c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>467 %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a468 ret <8 x i16> %r469}470 471define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) {472; CHECK-LABEL: unsigned_sat_constant_v4i32_using_min:473; CHECK: # %bb.0:474; CHECK-NEXT: addis 3, 2, .LCPI30_0@toc@ha475; CHECK-NEXT: addi 3, 3, .LCPI30_0@toc@l476; CHECK-NEXT: lxvd2x 35, 0, 3477; CHECK-NEXT: addis 3, 2, .LCPI30_1@toc@ha478; CHECK-NEXT: addi 3, 3, .LCPI30_1@toc@l479; CHECK-NEXT: vminuw 2, 2, 3480; CHECK-NEXT: lxvd2x 35, 0, 3481; CHECK-NEXT: vadduwm 2, 2, 3482; CHECK-NEXT: blr483 %c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>484 %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 -43, i32 -43, i32 -43, i32 -43>485 %r = add <4 x i32> %s, <i32 42, i32 42, i32 42, i32 42>486 ret <4 x i32> %r487}488 489define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {490; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:491; CHECK: # %bb.0:492; CHECK-NEXT: addis 3, 2, .LCPI31_0@toc@ha493; CHECK-NEXT: addi 3, 3, .LCPI31_0@toc@l494; CHECK-NEXT: lxvd2x 35, 0, 3495; CHECK-NEXT: vadduws 2, 2, 3496; CHECK-NEXT: blr497 %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>498 %c = icmp ugt <4 x i32> %x, %a499 %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a500 ret <4 x i32> %r501}502 503define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {504; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:505; CHECK: # %bb.0:506; CHECK-NEXT: addis 3, 2, .LCPI32_0@toc@ha507; CHECK-NEXT: addi 3, 3, .LCPI32_0@toc@l508; CHECK-NEXT: lxvd2x 35, 0, 3509; CHECK-NEXT: vadduws 2, 2, 3510; CHECK-NEXT: blr511 %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>512 %c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>513 %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a514 ret <4 x i32> %r515}516 517define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {518; CHECK-LABEL: unsigned_sat_constant_v2i64_using_min:519; CHECK: # %bb.0:520; CHECK-NEXT: addis 3, 2, .LCPI33_0@toc@ha521; CHECK-NEXT: addi 3, 3, .LCPI33_0@toc@l522; CHECK-NEXT: lxvd2x 35, 0, 3523; CHECK-NEXT: addis 3, 2, .LCPI33_1@toc@ha524; CHECK-NEXT: addi 3, 3, .LCPI33_1@toc@l525; CHECK-NEXT: vminud 2, 2, 3526; CHECK-NEXT: lxvd2x 35, 0, 3527; CHECK-NEXT: vaddudm 2, 2, 3528; CHECK-NEXT: blr529 %c = icmp ult <2 x i64> %x, <i64 -43, i64 -43>530 %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> <i64 -43, i64 -43>531 %r = add <2 x i64> %s, <i64 42, i64 42>532 ret <2 x i64> %r533}534 535define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {536; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:537; CHECK: # %bb.0:538; CHECK-NEXT: addis 3, 2, .LCPI34_0@toc@ha539; CHECK-NEXT: addi 3, 3, .LCPI34_0@toc@l540; CHECK-NEXT: lxvd2x 35, 0, 3541; CHECK-NEXT: vaddudm 3, 2, 3542; CHECK-NEXT: vcmpgtud 2, 2, 3543; CHECK-NEXT: xxlor 34, 34, 35544; CHECK-NEXT: blr545 %a = add <2 x i64> %x, <i64 42, i64 42>546 %c = icmp ugt <2 x i64> %x, %a547 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a548 ret <2 x i64> %r549}550 551define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {552; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:553; CHECK: # %bb.0:554; CHECK-NEXT: addis 3, 2, .LCPI35_0@toc@ha555; CHECK-NEXT: addi 3, 3, .LCPI35_0@toc@l556; CHECK-NEXT: lxvd2x 35, 0, 3557; CHECK-NEXT: addis 3, 2, .LCPI35_1@toc@ha558; CHECK-NEXT: addi 3, 3, .LCPI35_1@toc@l559; CHECK-NEXT: lxvd2x 36, 0, 3560; CHECK-NEXT: vaddudm 3, 2, 3561; CHECK-NEXT: vcmpgtud 2, 2, 4562; CHECK-NEXT: xxlor 34, 34, 35563; CHECK-NEXT: blr564 %a = add <2 x i64> %x, <i64 42, i64 42>565 %c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>566 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a567 ret <2 x i64> %r568}569 570define <16 x i8> @unsigned_sat_variable_v16i8_using_min(<16 x i8> %x, <16 x i8> %y) {571; CHECK-LABEL: unsigned_sat_variable_v16i8_using_min:572; CHECK: # %bb.0:573; CHECK-NEXT: xxlnor 36, 35, 35574; CHECK-NEXT: vminub 2, 2, 4575; CHECK-NEXT: vaddubm 2, 2, 3576; CHECK-NEXT: blr577 %noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>578 %c = icmp ult <16 x i8> %x, %noty579 %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %noty580 %r = add <16 x i8> %s, %y581 ret <16 x i8> %r582}583 584define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_sum(<16 x i8> %x, <16 x i8> %y) {585; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum:586; CHECK: # %bb.0:587; CHECK-NEXT: vaddubs 2, 2, 3588; CHECK-NEXT: blr589 %a = add <16 x i8> %x, %y590 %c = icmp ugt <16 x i8> %x, %a591 %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a592 ret <16 x i8> %r593}594 595define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_notval(<16 x i8> %x, <16 x i8> %y) {596; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval:597; CHECK: # %bb.0:598; CHECK-NEXT: xxlnor 36, 35, 35599; CHECK-NEXT: vaddubm 3, 2, 3600; CHECK-NEXT: vcmpgtub 2, 2, 4601; CHECK-NEXT: xxlor 34, 34, 35602; CHECK-NEXT: blr603 %noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>604 %a = add <16 x i8> %x, %y605 %c = icmp ugt <16 x i8> %x, %noty606 %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a607 ret <16 x i8> %r608}609 610define <8 x i16> @unsigned_sat_variable_v8i16_using_min(<8 x i16> %x, <8 x i16> %y) {611; CHECK-LABEL: unsigned_sat_variable_v8i16_using_min:612; CHECK: # %bb.0:613; CHECK-NEXT: xxlnor 36, 35, 35614; CHECK-NEXT: vminuh 2, 2, 4615; CHECK-NEXT: vadduhm 2, 2, 3616; CHECK-NEXT: blr617 %noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>618 %c = icmp ult <8 x i16> %x, %noty619 %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %noty620 %r = add <8 x i16> %s, %y621 ret <8 x i16> %r622}623 624define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_sum(<8 x i16> %x, <8 x i16> %y) {625; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum:626; CHECK: # %bb.0:627; CHECK-NEXT: vadduhs 2, 2, 3628; CHECK-NEXT: blr629 %a = add <8 x i16> %x, %y630 %c = icmp ugt <8 x i16> %x, %a631 %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a632 ret <8 x i16> %r633}634 635define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8 x i16> %y) {636; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval:637; CHECK: # %bb.0:638; CHECK-NEXT: xxlnor 36, 35, 35639; CHECK-NEXT: vadduhm 3, 2, 3640; CHECK-NEXT: vcmpgtuh 2, 2, 4641; CHECK-NEXT: xxlor 34, 34, 35642; CHECK-NEXT: blr643 %noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>644 %a = add <8 x i16> %x, %y645 %c = icmp ugt <8 x i16> %x, %noty646 %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a647 ret <8 x i16> %r648}649 650define <4 x i32> @unsigned_sat_variable_v4i32_using_min(<4 x i32> %x, <4 x i32> %y) {651; CHECK-LABEL: unsigned_sat_variable_v4i32_using_min:652; CHECK: # %bb.0:653; CHECK-NEXT: xxlnor 36, 35, 35654; CHECK-NEXT: vminuw 2, 2, 4655; CHECK-NEXT: vadduwm 2, 2, 3656; CHECK-NEXT: blr657 %noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>658 %c = icmp ult <4 x i32> %x, %noty659 %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %noty660 %r = add <4 x i32> %s, %y661 ret <4 x i32> %r662}663 664define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_sum(<4 x i32> %x, <4 x i32> %y) {665; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum:666; CHECK: # %bb.0:667; CHECK-NEXT: vadduws 2, 2, 3668; CHECK-NEXT: blr669 %a = add <4 x i32> %x, %y670 %c = icmp ugt <4 x i32> %x, %a671 %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a672 ret <4 x i32> %r673}674 675define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4 x i32> %y) {676; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval:677; CHECK: # %bb.0:678; CHECK-NEXT: xxlnor 36, 35, 35679; CHECK-NEXT: vadduwm 3, 2, 3680; CHECK-NEXT: vcmpgtuw 2, 2, 4681; CHECK-NEXT: xxlor 34, 34, 35682; CHECK-NEXT: blr683 %noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>684 %a = add <4 x i32> %x, %y685 %c = icmp ugt <4 x i32> %x, %noty686 %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a687 ret <4 x i32> %r688}689 690define <2 x i64> @unsigned_sat_variable_v2i64_using_min(<2 x i64> %x, <2 x i64> %y) {691; CHECK-LABEL: unsigned_sat_variable_v2i64_using_min:692; CHECK: # %bb.0:693; CHECK-NEXT: xxlnor 36, 35, 35694; CHECK-NEXT: vminud 2, 2, 4695; CHECK-NEXT: vaddudm 2, 2, 3696; CHECK-NEXT: blr697 %noty = xor <2 x i64> %y, <i64 -1, i64 -1>698 %c = icmp ult <2 x i64> %x, %noty699 %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %noty700 %r = add <2 x i64> %s, %y701 ret <2 x i64> %r702}703 704define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_sum(<2 x i64> %x, <2 x i64> %y) {705; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum:706; CHECK: # %bb.0:707; CHECK-NEXT: vaddudm 3, 2, 3708; CHECK-NEXT: vcmpgtud 2, 2, 3709; CHECK-NEXT: xxlor 34, 34, 35710; CHECK-NEXT: blr711 %a = add <2 x i64> %x, %y712 %c = icmp ugt <2 x i64> %x, %a713 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a714 ret <2 x i64> %r715}716 717define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2 x i64> %y) {718; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval:719; CHECK: # %bb.0:720; CHECK-NEXT: xxlnor 36, 35, 35721; CHECK-NEXT: vaddudm 3, 2, 3722; CHECK-NEXT: vcmpgtud 2, 2, 4723; CHECK-NEXT: xxlor 34, 34, 35724; CHECK-NEXT: blr725 %noty = xor <2 x i64> %y, <i64 -1, i64 -1>726 %a = add <2 x i64> %x, %y727 %c = icmp ugt <2 x i64> %x, %noty728 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a729 ret <2 x i64> %r730}731 732declare <4 x i128> @llvm.sadd.sat.v4i128(<4 x i128> %a, <4 x i128> %b);733 734define <4 x i128> @sadd(<4 x i128> %a, <4 x i128> %b) local_unnamed_addr {735; CHECK-LABEL: sadd:736; CHECK: # %bb.0:737; CHECK-NEXT: vadduqm 0, 2, 6738; CHECK-NEXT: vadduqm 10, 4, 8739; CHECK-NEXT: mfocrf 12, 32740; CHECK-NEXT: stw 12, 8(1)741; CHECK-NEXT: xxswapd 0, 34742; CHECK-NEXT: xxswapd 4, 36743; CHECK-NEXT: vadduqm 1, 3, 7744; CHECK-NEXT: vadduqm 11, 5, 9745; CHECK-NEXT: mffprd 3, 0746; CHECK-NEXT: mffprd 6, 4747; CHECK-NEXT: lwz 12, 8(1)748; CHECK-NEXT: xxswapd 2, 35749; CHECK-NEXT: xxswapd 5, 37750; CHECK-NEXT: mffprd 4, 2751; CHECK-NEXT: xxswapd 1, 32752; CHECK-NEXT: xxswapd 6, 42753; CHECK-NEXT: mffprd 5, 1754; CHECK-NEXT: cmpld 6, 5, 3755; CHECK-NEXT: mffprd 7, 6756; CHECK-NEXT: xxswapd 3, 33757; CHECK-NEXT: xxswapd 7, 43758; CHECK-NEXT: mffprd 3, 3759; CHECK-NEXT: cmpld 5, 7, 6760; CHECK-NEXT: mffprd 6, 5761; CHECK-NEXT: mffprd 7, 7762; CHECK-NEXT: mfvsrd 5, 36763; CHECK-NEXT: cmpld 3, 4764; CHECK-NEXT: mfvsrd 3, 34765; CHECK-NEXT: cmpld 1, 7, 6766; CHECK-NEXT: mfvsrd 7, 32767; CHECK-NEXT: mfvsrd 4, 35768; CHECK-NEXT: mfvsrd 6, 37769; CHECK-NEXT: cmpld 7, 7, 3770; CHECK-NEXT: cmpd 2, 7, 3771; CHECK-NEXT: mfvsrd 3, 33772; CHECK-NEXT: crandc 21, 8, 30773; CHECK-NEXT: crand 22, 30, 24774; CHECK-NEXT: cmpld 6, 3, 4775; CHECK-NEXT: cmpd 7, 3, 4776; CHECK-NEXT: mfvsrd 4, 42777; CHECK-NEXT: sradi 3, 3, 63778; CHECK-NEXT: mtocrf 32, 12779; CHECK-NEXT: crnor 21, 22, 21780; CHECK-NEXT: crandc 23, 28, 26781; CHECK-NEXT: crand 24, 26, 0782; CHECK-NEXT: cmpld 4, 5783; CHECK-NEXT: cmpd 7, 4, 5784; CHECK-NEXT: mfvsrd 5, 43785; CHECK-NEXT: crnor 22, 24, 23786; CHECK-NEXT: mtfprd 5, 3787; CHECK-NEXT: sradi 4, 4, 63788; CHECK-NEXT: mtfprd 6, 4789; CHECK-NEXT: crandc 25, 28, 2790; CHECK-NEXT: crand 20, 2, 20791; CHECK-NEXT: cmpld 5, 6792; CHECK-NEXT: cmpd 7, 5, 6793; CHECK-NEXT: mfvsrd 6, 38794; CHECK-NEXT: sradi 5, 5, 63795; CHECK-NEXT: crnor 20, 20, 25796; CHECK-NEXT: mtfprd 7, 5797; CHECK-NEXT: sradi 6, 6, 63798; CHECK-NEXT: crandc 26, 28, 2799; CHECK-NEXT: crand 27, 2, 4800; CHECK-NEXT: crnor 23, 27, 26801; CHECK-NEXT: mtfprd 0, 6802; CHECK-NEXT: mfvsrd 6, 39803; CHECK-NEXT: sradi 6, 6, 63804; CHECK-NEXT: mtfprd 1, 6805; CHECK-NEXT: mfvsrd 6, 40806; CHECK-NEXT: sradi 6, 6, 63807; CHECK-NEXT: mtfprd 2, 6808; CHECK-NEXT: mfvsrd 6, 41809; CHECK-NEXT: sradi 6, 6, 63810; CHECK-NEXT: mtfprd 3, 6811; CHECK-NEXT: sradi 6, 7, 63812; CHECK-NEXT: mtfprd 4, 6813; CHECK-NEXT: li 6, -1814; CHECK-NEXT: isel 3, 0, 6, 21815; CHECK-NEXT: isel 4, 0, 6, 22816; CHECK-NEXT: isel 5, 0, 6, 20817; CHECK-NEXT: isel 6, 0, 6, 23818; CHECK-NEXT: mtfprd 8, 3819; CHECK-NEXT: addis 3, 2, .LCPI48_0@toc@ha820; CHECK-NEXT: mtfprd 10, 4821; CHECK-NEXT: mtfprd 11, 5822; CHECK-NEXT: mtfprd 12, 6823; CHECK-NEXT: addi 3, 3, .LCPI48_0@toc@l824; CHECK-NEXT: lxvd2x 9, 0, 3825; CHECK-NEXT: xxspltd 45, 6, 0826; CHECK-NEXT: xxspltd 46, 7, 0827; CHECK-NEXT: xxspltd 34, 0, 0828; CHECK-NEXT: xxspltd 40, 5, 0829; CHECK-NEXT: xxspltd 35, 1, 0830; CHECK-NEXT: xxspltd 36, 2, 0831; CHECK-NEXT: xxspltd 38, 3, 0832; CHECK-NEXT: xxspltd 39, 4, 0833; CHECK-NEXT: xxspltd 41, 8, 0834; CHECK-NEXT: xxspltd 44, 10, 0835; CHECK-NEXT: xxspltd 47, 11, 0836; CHECK-NEXT: xxspltd 48, 12, 0837; CHECK-NEXT: xxlxor 0, 34, 41838; CHECK-NEXT: xxlxor 1, 35, 44839; CHECK-NEXT: xxswapd 37, 9840; CHECK-NEXT: xxlxor 2, 39, 37841; CHECK-NEXT: xxlxor 3, 40, 37842; CHECK-NEXT: xxsel 34, 32, 2, 0843; CHECK-NEXT: xxsel 35, 33, 3, 1844; CHECK-NEXT: xxlxor 0, 36, 47845; CHECK-NEXT: xxlxor 1, 45, 37846; CHECK-NEXT: xxsel 36, 42, 1, 0847; CHECK-NEXT: xxlxor 0, 38, 48848; CHECK-NEXT: xxlxor 1, 46, 37849; CHECK-NEXT: xxsel 37, 43, 1, 0850; CHECK-NEXT: blr851 %c = call <4 x i128> @llvm.sadd.sat.v4i128(<4 x i128> %a, <4 x i128> %b)852 ret <4 x i128> %c853}854 855define i64 @unsigned_sat_constant_i64_with_single_use(i64 %x) {856; CHECK-LABEL: unsigned_sat_constant_i64_with_single_use:857; CHECK: # %bb.0:858; CHECK-NEXT: li 4, 4859; CHECK-NEXT: subc 3, 3, 4860; CHECK-NEXT: li 4, 0861; CHECK-NEXT: addze. 4, 4862; CHECK-NEXT: iseleq 3, 0, 3863; CHECK-NEXT: blr864 %umin = call i64 @llvm.umin.i64(i64 %x, i64 4)865 %sub = sub i64 %x, %umin866 ret i64 %sub867}868 869define i64 @unsigned_sat_constant_i64_with_multiple_use(i64 %x, i64 %y) {870; CHECK-LABEL: unsigned_sat_constant_i64_with_multiple_use:871; CHECK: # %bb.0:872; CHECK-NEXT: cmpldi 3, 4873; CHECK-NEXT: li 5, 4874; CHECK-NEXT: isellt 5, 3, 5875; CHECK-NEXT: sub 3, 3, 5876; CHECK-NEXT: add 4, 4, 5877; CHECK-NEXT: mulld 3, 3, 4878; CHECK-NEXT: blr879 %umin = call i64 @llvm.umin.i64(i64 %x, i64 4)880 %sub = sub i64 %x, %umin881 %add = add i64 %y, %umin882 %res = mul i64 %sub, %add883 ret i64 %res884}885 886declare i64 @llvm.umin.i64(i64, i64)887