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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: %s -o - -verify-machineinstrs -mcpu=pwr9 | FileCheck %s4 5define <4 x i32> @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %aa, ptr %FromVSCR) {6; CHECK-LABEL: test:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vsumsws v5, v2, v39; CHECK-NEXT: xxlxor vs32, vs32, vs3210; CHECK-NEXT: mtvscr v011; CHECK-NEXT: vadduwm v0, v3, v212; CHECK-NEXT: vpkswus v2, v2, v313; CHECK-NEXT: mfvscr v114; CHECK-NEXT: stxv vs33, 0(r9)15; CHECK-NEXT: vpkswus v3, v3, v416; CHECK-NEXT: vadduwm v4, v0, v517; CHECK-NEXT: vadduwm v2, v4, v218; CHECK-NEXT: vadduwm v2, v2, v319; CHECK-NEXT: blr20entry:21 %0 = tail call <4 x i32> @llvm.ppc.altivec.vsumsws(<4 x i32> %a, <4 x i32> %b)22 tail call void @llvm.ppc.altivec.mtvscr(<4 x i32> zeroinitializer)23 %add = add <4 x i32> %b, %a24 %1 = tail call <8 x i16> @llvm.ppc.altivec.vpkswus(<4 x i32> %a, <4 x i32> %b)25 %2 = bitcast <8 x i16> %1 to <4 x i32>26 %3 = tail call <8 x i16> @llvm.ppc.altivec.mfvscr()27 store <8 x i16> %3, ptr %FromVSCR, align 1628 %4 = tail call <8 x i16> @llvm.ppc.altivec.vpkswus(<4 x i32> %b, <4 x i32> %aa)29 %5 = bitcast <8 x i16> %4 to <4 x i32>30 %add1 = add <4 x i32> %add, %031 %add2 = add <4 x i32> %add1, %232 %add3 = add <4 x i32> %add2, %533 ret <4 x i32> %add334}35 36declare <4 x i32> @llvm.ppc.altivec.vsumsws(<4 x i32>, <4 x i32>) #137 38declare void @llvm.ppc.altivec.mtvscr(<4 x i32>) #139 40declare <8 x i16> @llvm.ppc.altivec.vpkswus(<4 x i32>, <4 x i32>) #141 42declare <8 x i16> @llvm.ppc.altivec.mfvscr() #143 44