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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O3 -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \3; RUN: -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s4define dso_local <16 x i8 > @vectorsaddb(<16 x i8 > %a, <16 x i8 > %b) {5; CHECK-LABEL: vectorsaddb:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: vaddsbs v2, v2, v38; CHECK-NEXT: blr9entry:10 %call = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %a, <16 x i8> %b)11 ret <16 x i8> %call12}13 14define dso_local <16 x i8 > @vectorssubb(<16 x i8 > %a, <16 x i8 > %b) {15; CHECK-LABEL: vectorssubb:16; CHECK: # %bb.0: # %entry17; CHECK-NEXT: vsubsbs v2, v2, v318; CHECK-NEXT: blr19entry:20 %call = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %a, <16 x i8> %b)21 ret <16 x i8> %call22}23 24define dso_local <16 x i8 > @vectoruaddb(<16 x i8 > %a, <16 x i8 > %b) {25; CHECK-LABEL: vectoruaddb:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vaddubs v2, v2, v328; CHECK-NEXT: blr29entry:30 %call = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %a, <16 x i8> %b)31 ret <16 x i8> %call32}33 34define dso_local <16 x i8 > @vectorusubb(<16 x i8 > %a, <16 x i8 > %b) {35; CHECK-LABEL: vectorusubb:36; CHECK: # %bb.0: # %entry37; CHECK-NEXT: vsububs v2, v2, v338; CHECK-NEXT: blr39entry:40 %call = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %a, <16 x i8> %b)41 ret <16 x i8> %call42}43 44define dso_local <8 x i16 > @vectorsaddh(<8 x i16 > %a, <8 x i16 > %b) {45; CHECK-LABEL: vectorsaddh:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: vaddshs v2, v2, v348; CHECK-NEXT: blr49entry:50 %call = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %a, <8 x i16> %b)51 ret <8 x i16> %call52}53 54define dso_local <8 x i16 > @vectorssubh(<8 x i16 > %a, <8 x i16 > %b) {55; CHECK-LABEL: vectorssubh:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: vsubshs v2, v2, v358; CHECK-NEXT: blr59entry:60 %call = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a, <8 x i16> %b)61 ret <8 x i16> %call62}63 64define dso_local <8 x i16 > @vectoruaddh(<8 x i16 > %a, <8 x i16 > %b) {65; CHECK-LABEL: vectoruaddh:66; CHECK: # %bb.0: # %entry67; CHECK-NEXT: vadduhs v2, v2, v368; CHECK-NEXT: blr69entry:70 %call = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %a, <8 x i16> %b)71 ret <8 x i16> %call72}73 74define dso_local <8 x i16 > @vectorusubh(<8 x i16 > %a, <8 x i16 > %b) {75; CHECK-LABEL: vectorusubh:76; CHECK: # %bb.0: # %entry77; CHECK-NEXT: vsubuhs v2, v2, v378; CHECK-NEXT: blr79entry:80 %call = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %a, <8 x i16> %b)81 ret <8 x i16> %call82}83 84define dso_local <4 x i32 > @vectorsaddw(<4 x i32 > %a, <4 x i32 > %b) {85; CHECK-LABEL: vectorsaddw:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vaddsws v2, v2, v388; CHECK-NEXT: blr89entry:90 %call = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)91 ret <4 x i32> %call92}93 94define dso_local <4 x i32 > @vectorssubw(<4 x i32 > %a, <4 x i32 > %b) {95; CHECK-LABEL: vectorssubw:96; CHECK: # %bb.0: # %entry97; CHECK-NEXT: vsubsws v2, v2, v398; CHECK-NEXT: blr99entry:100 %call = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)101 ret <4 x i32> %call102}103 104define dso_local <4 x i32 > @vectoruaddw(<4 x i32 > %a, <4 x i32 > %b) {105; CHECK-LABEL: vectoruaddw:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: vadduws v2, v2, v3108; CHECK-NEXT: blr109entry:110 %call = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)111 ret <4 x i32> %call112}113 114define dso_local <4 x i32 > @vectorusubw(<4 x i32 > %a, <4 x i32 > %b) {115; CHECK-LABEL: vectorusubw:116; CHECK: # %bb.0: # %entry117; CHECK-NEXT: vsubuws v2, v2, v3118; CHECK-NEXT: blr119entry:120 %call = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)121 ret <4 x i32> %call122}123 124declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)125declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)126declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)127declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>)128declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)129declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)130declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)131declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)132declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)133declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)134declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)135declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>)136