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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \3; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE4; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \5; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE6; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \7; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE8; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \9; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE10 11define i8 @scalar_to_vector_half(ptr nocapture readonly %ad) {12; P9LE-LABEL: scalar_to_vector_half:13; P9LE: # %bb.0: # %entry14; P9LE-NEXT: lxsihzx v2, 0, r315; P9LE-NEXT: li r3, 016; P9LE-NEXT: vsplth v2, v2, 317; P9LE-NEXT: vextubrx r3, r3, v218; P9LE-NEXT: blr19;20; P9BE-LABEL: scalar_to_vector_half:21; P9BE: # %bb.0: # %entry22; P9BE-NEXT: lxsihzx v2, 0, r323; P9BE-NEXT: li r3, 024; P9BE-NEXT: vsplth v2, v2, 325; P9BE-NEXT: vextublx r3, r3, v226; P9BE-NEXT: blr27;28; P8LE-LABEL: scalar_to_vector_half:29; P8LE: # %bb.0: # %entry30; P8LE-NEXT: lhz r3, 0(r3)31; P8LE-NEXT: mtfprd f0, r332; P8LE-NEXT: mffprd r3, f033; P8LE-NEXT: clrldi r3, r3, 5634; P8LE-NEXT: blr35;36; P8BE-LABEL: scalar_to_vector_half:37; P8BE: # %bb.0: # %entry38; P8BE-NEXT: lhz r3, 0(r3)39; P8BE-NEXT: sldi r3, r3, 4840; P8BE-NEXT: mtfprd f0, r341; P8BE-NEXT: mffprd r3, f042; P8BE-NEXT: rldicl r3, r3, 8, 5643; P8BE-NEXT: blr44entry:45 %0 = load <2 x i8>, ptr %ad, align 146 %1 = extractelement <2 x i8> %0, i32 047 ret i8 %148}49 50