512 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -ppc-convert-rr-to-ri=true \3; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr | FileCheck %s4 5define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) {6; CHECK-LABEL: all_bits_clear:7; CHECK: # %bb.0:8; CHECK-NEXT: or r3, r3, r49; CHECK-NEXT: cntlzw r3, r310; CHECK-NEXT: srwi r3, r3, 511; CHECK-NEXT: blr12 %a = icmp eq i32 %P, 013 %b = icmp eq i32 %Q, 014 %c = and i1 %a, %b15 ret i1 %c16}17 18define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) {19; CHECK-LABEL: all_sign_bits_clear:20; CHECK: # %bb.0:21; CHECK-NEXT: or r3, r3, r422; CHECK-NEXT: rlwinm r3, r3, 1, 31, 3123; CHECK-NEXT: xori r3, r3, 124; CHECK-NEXT: blr25 %a = icmp sgt i32 %P, -126 %b = icmp sgt i32 %Q, -127 %c = and i1 %a, %b28 ret i1 %c29}30 31define zeroext i1 @all_bits_set(i32 %P, i32 %Q) {32; CHECK-LABEL: all_bits_set:33; CHECK: # %bb.0:34; CHECK-NEXT: and r3, r3, r435; CHECK-NEXT: li r4, -136; CHECK-NEXT: xor r3, r3, r437; CHECK-NEXT: cntlzw r3, r338; CHECK-NEXT: srwi r3, r3, 539; CHECK-NEXT: blr40 %a = icmp eq i32 %P, -141 %b = icmp eq i32 %Q, -142 %c = and i1 %a, %b43 ret i1 %c44}45 46define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) {47; CHECK-LABEL: all_sign_bits_set:48; CHECK: # %bb.0:49; CHECK-NEXT: and r3, r3, r450; CHECK-NEXT: rlwinm r3, r3, 1, 31, 3151; CHECK-NEXT: blr52 %a = icmp slt i32 %P, 053 %b = icmp slt i32 %Q, 054 %c = and i1 %a, %b55 ret i1 %c56}57 58define zeroext i1 @any_bits_set(i32 %P, i32 %Q) {59; CHECK-LABEL: any_bits_set:60; CHECK: # %bb.0:61; CHECK-NEXT: or r3, r3, r462; CHECK-NEXT: cntlzw r3, r363; CHECK-NEXT: srwi r3, r3, 564; CHECK-NEXT: xori r3, r3, 165; CHECK-NEXT: blr66 %a = icmp ne i32 %P, 067 %b = icmp ne i32 %Q, 068 %c = or i1 %a, %b69 ret i1 %c70}71 72define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) {73; CHECK-LABEL: any_sign_bits_set:74; CHECK: # %bb.0:75; CHECK-NEXT: or r3, r3, r476; CHECK-NEXT: rlwinm r3, r3, 1, 31, 3177; CHECK-NEXT: blr78 %a = icmp slt i32 %P, 079 %b = icmp slt i32 %Q, 080 %c = or i1 %a, %b81 ret i1 %c82}83 84define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) {85; CHECK-LABEL: any_bits_clear:86; CHECK: # %bb.0:87; CHECK-NEXT: and r3, r3, r488; CHECK-NEXT: li r4, -189; CHECK-NEXT: xor r3, r3, r490; CHECK-NEXT: cntlzw r3, r391; CHECK-NEXT: srwi r3, r3, 592; CHECK-NEXT: xori r3, r3, 193; CHECK-NEXT: blr94 %a = icmp ne i32 %P, -195 %b = icmp ne i32 %Q, -196 %c = or i1 %a, %b97 ret i1 %c98}99 100define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) {101; CHECK-LABEL: any_sign_bits_clear:102; CHECK: # %bb.0:103; CHECK-NEXT: and r3, r3, r4104; CHECK-NEXT: rlwinm r3, r3, 1, 31, 31105; CHECK-NEXT: xori r3, r3, 1106; CHECK-NEXT: blr107 %a = icmp sgt i32 %P, -1108 %b = icmp sgt i32 %Q, -1109 %c = or i1 %a, %b110 ret i1 %c111}112 113; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0114define i32 @all_bits_clear_branch(ptr %P, ptr %Q) {115; CHECK-LABEL: all_bits_clear_branch:116; CHECK: # %bb.0: # %entry117; CHECK-NEXT: or. r3, r3, r4118; CHECK-NEXT: bne cr0, .LBB8_2119; CHECK-NEXT: # %bb.1: # %bb1120; CHECK-NEXT: li r3, 4121; CHECK-NEXT: blr122; CHECK-NEXT: .LBB8_2: # %return123; CHECK-NEXT: li r3, 192124; CHECK-NEXT: blr125entry:126 %a = icmp eq ptr %P, null127 %b = icmp eq ptr %Q, null128 %c = and i1 %a, %b129 br i1 %c, label %bb1, label %return130 131bb1:132 ret i32 4133 134return:135 ret i32 192136}137 138define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) {139; CHECK-LABEL: all_sign_bits_clear_branch:140; CHECK: # %bb.0: # %entry141; CHECK-NEXT: or r3, r3, r4142; CHECK-NEXT: cmpwi r3, 0143; CHECK-NEXT: blt cr0, .LBB9_2144; CHECK-NEXT: # %bb.1: # %bb1145; CHECK-NEXT: li r3, 4146; CHECK-NEXT: blr147; CHECK-NEXT: .LBB9_2: # %return148; CHECK-NEXT: li r3, 192149; CHECK-NEXT: blr150entry:151 %a = icmp sgt i32 %P, -1152 %b = icmp sgt i32 %Q, -1153 %c = and i1 %a, %b154 br i1 %c, label %bb1, label %return155 156bb1:157 ret i32 4158 159return:160 ret i32 192161}162 163define i32 @all_bits_set_branch(i32 %P, i32 %Q) {164; CHECK-LABEL: all_bits_set_branch:165; CHECK: # %bb.0: # %entry166; CHECK-NEXT: and r3, r3, r4167; CHECK-NEXT: cmpwi r3, -1168; CHECK-NEXT: bne cr0, .LBB10_2169; CHECK-NEXT: # %bb.1: # %bb1170; CHECK-NEXT: li r3, 4171; CHECK-NEXT: blr172; CHECK-NEXT: .LBB10_2: # %return173; CHECK-NEXT: li r3, 192174; CHECK-NEXT: blr175entry:176 %a = icmp eq i32 %P, -1177 %b = icmp eq i32 %Q, -1178 %c = and i1 %a, %b179 br i1 %c, label %bb1, label %return180 181bb1:182 ret i32 4183 184return:185 ret i32 192186}187 188define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) {189; CHECK-LABEL: all_sign_bits_set_branch:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: and r3, r3, r4192; CHECK-NEXT: cmpwi r3, -1193; CHECK-NEXT: bgt cr0, .LBB11_2194; CHECK-NEXT: # %bb.1: # %bb1195; CHECK-NEXT: li r3, 4196; CHECK-NEXT: blr197; CHECK-NEXT: .LBB11_2: # %return198; CHECK-NEXT: li r3, 192199; CHECK-NEXT: blr200entry:201 %a = icmp slt i32 %P, 0202 %b = icmp slt i32 %Q, 0203 %c = and i1 %a, %b204 br i1 %c, label %bb1, label %return205 206bb1:207 ret i32 4208 209return:210 ret i32 192211}212 213; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0214define i32 @any_bits_set_branch(ptr %P, ptr %Q) {215; CHECK-LABEL: any_bits_set_branch:216; CHECK: # %bb.0: # %entry217; CHECK-NEXT: or. r3, r3, r4218; CHECK-NEXT: beq cr0, .LBB12_2219; CHECK-NEXT: # %bb.1: # %bb1220; CHECK-NEXT: li r3, 4221; CHECK-NEXT: blr222; CHECK-NEXT: .LBB12_2: # %return223; CHECK-NEXT: li r3, 192224; CHECK-NEXT: blr225entry:226 %a = icmp ne ptr %P, null227 %b = icmp ne ptr %Q, null228 %c = or i1 %a, %b229 br i1 %c, label %bb1, label %return230 231bb1:232 ret i32 4233 234return:235 ret i32 192236}237 238define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) {239; CHECK-LABEL: any_sign_bits_set_branch:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: or r3, r3, r4242; CHECK-NEXT: cmpwi r3, -1243; CHECK-NEXT: bgt cr0, .LBB13_2244; CHECK-NEXT: # %bb.1: # %bb1245; CHECK-NEXT: li r3, 4246; CHECK-NEXT: blr247; CHECK-NEXT: .LBB13_2: # %return248; CHECK-NEXT: li r3, 192249; CHECK-NEXT: blr250entry:251 %a = icmp slt i32 %P, 0252 %b = icmp slt i32 %Q, 0253 %c = or i1 %a, %b254 br i1 %c, label %bb1, label %return255 256bb1:257 ret i32 4258 259return:260 ret i32 192261}262 263define i32 @any_bits_clear_branch(i32 %P, i32 %Q) {264; CHECK-LABEL: any_bits_clear_branch:265; CHECK: # %bb.0: # %entry266; CHECK-NEXT: and r3, r3, r4267; CHECK-NEXT: cmpwi r3, -1268; CHECK-NEXT: beq cr0, .LBB14_2269; CHECK-NEXT: # %bb.1: # %bb1270; CHECK-NEXT: li r3, 4271; CHECK-NEXT: blr272; CHECK-NEXT: .LBB14_2: # %return273; CHECK-NEXT: li r3, 192274; CHECK-NEXT: blr275entry:276 %a = icmp ne i32 %P, -1277 %b = icmp ne i32 %Q, -1278 %c = or i1 %a, %b279 br i1 %c, label %bb1, label %return280 281bb1:282 ret i32 4283 284return:285 ret i32 192286}287 288define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) {289; CHECK-LABEL: any_sign_bits_clear_branch:290; CHECK: # %bb.0: # %entry291; CHECK-NEXT: and r3, r3, r4292; CHECK-NEXT: cmpwi r3, 0293; CHECK-NEXT: blt cr0, .LBB15_2294; CHECK-NEXT: # %bb.1: # %bb1295; CHECK-NEXT: li r3, 4296; CHECK-NEXT: blr297; CHECK-NEXT: .LBB15_2: # %return298; CHECK-NEXT: li r3, 192299; CHECK-NEXT: blr300entry:301 %a = icmp sgt i32 %P, -1302 %b = icmp sgt i32 %Q, -1303 %c = or i1 %a, %b304 br i1 %c, label %bb1, label %return305 306bb1:307 ret i32 4308 309return:310 ret i32 192311}312 313define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {314; CHECK-LABEL: all_bits_clear_vec:315; CHECK: # %bb.0:316; CHECK-NEXT: xxlor v2, v2, v3317; CHECK-NEXT: xxlxor v3, v3, v3318; CHECK-NEXT: vcmpequw v2, v2, v3319; CHECK-NEXT: blr320 %a = icmp eq <4 x i32> %P, zeroinitializer321 %b = icmp eq <4 x i32> %Q, zeroinitializer322 %c = and <4 x i1> %a, %b323 ret <4 x i1> %c324}325 326define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {327; CHECK-LABEL: all_sign_bits_clear_vec:328; CHECK: # %bb.0:329; CHECK-NEXT: xxlor v2, v2, v3330; CHECK-NEXT: xxleqv v3, v3, v3331; CHECK-NEXT: vcmpgtsw v2, v2, v3332; CHECK-NEXT: blr333 %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>334 %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>335 %c = and <4 x i1> %a, %b336 ret <4 x i1> %c337}338 339define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {340; CHECK-LABEL: all_bits_set_vec:341; CHECK: # %bb.0:342; CHECK-NEXT: xxland v2, v2, v3343; CHECK-NEXT: xxleqv v3, v3, v3344; CHECK-NEXT: vcmpequw v2, v2, v3345; CHECK-NEXT: blr346 %a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>347 %b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>348 %c = and <4 x i1> %a, %b349 ret <4 x i1> %c350}351 352define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {353; CHECK-LABEL: all_sign_bits_set_vec:354; CHECK: # %bb.0:355; CHECK-NEXT: xxland v2, v2, v3356; CHECK-NEXT: xxlxor v3, v3, v3357; CHECK-NEXT: vcmpgtsw v2, v3, v2358; CHECK-NEXT: blr359 %a = icmp slt <4 x i32> %P, zeroinitializer360 %b = icmp slt <4 x i32> %Q, zeroinitializer361 %c = and <4 x i1> %a, %b362 ret <4 x i1> %c363}364 365define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {366; CHECK-LABEL: any_bits_set_vec:367; CHECK: # %bb.0:368; CHECK-NEXT: xxlor v2, v2, v3369; CHECK-NEXT: xxlxor v3, v3, v3370; CHECK-NEXT: vcmpequw v2, v2, v3371; CHECK-NEXT: xxlnor v2, v2, v2372; CHECK-NEXT: blr373 %a = icmp ne <4 x i32> %P, zeroinitializer374 %b = icmp ne <4 x i32> %Q, zeroinitializer375 %c = or <4 x i1> %a, %b376 ret <4 x i1> %c377}378 379define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {380; CHECK-LABEL: any_sign_bits_set_vec:381; CHECK: # %bb.0:382; CHECK-NEXT: xxlor v2, v2, v3383; CHECK-NEXT: xxlxor v3, v3, v3384; CHECK-NEXT: vcmpgtsw v2, v3, v2385; CHECK-NEXT: blr386 %a = icmp slt <4 x i32> %P, zeroinitializer387 %b = icmp slt <4 x i32> %Q, zeroinitializer388 %c = or <4 x i1> %a, %b389 ret <4 x i1> %c390}391 392define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {393; CHECK-LABEL: any_bits_clear_vec:394; CHECK: # %bb.0:395; CHECK-NEXT: xxland v2, v2, v3396; CHECK-NEXT: xxleqv v3, v3, v3397; CHECK-NEXT: vcmpequw v2, v2, v3398; CHECK-NEXT: xxlnor v2, v2, v2399; CHECK-NEXT: blr400 %a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>401 %b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>402 %c = or <4 x i1> %a, %b403 ret <4 x i1> %c404}405 406define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {407; CHECK-LABEL: any_sign_bits_clear_vec:408; CHECK: # %bb.0:409; CHECK-NEXT: xxland v2, v2, v3410; CHECK-NEXT: xxleqv v3, v3, v3411; CHECK-NEXT: vcmpgtsw v2, v2, v3412; CHECK-NEXT: blr413 %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>414 %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>415 %c = or <4 x i1> %a, %b416 ret <4 x i1> %c417}418 419define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {420; CHECK-LABEL: ne_neg1_and_ne_zero:421; CHECK: # %bb.0:422; CHECK-NEXT: addi r3, r3, 1423; CHECK-NEXT: li r4, 1424; CHECK-NEXT: subfic r3, r3, 1425; CHECK-NEXT: subfe r3, r4, r4426; CHECK-NEXT: neg r3, r3427; CHECK-NEXT: blr428 %cmp1 = icmp ne i64 %x, -1429 %cmp2 = icmp ne i64 %x, 0430 %and = and i1 %cmp1, %cmp2431 ret i1 %and432}433 434; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401435 436define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {437; CHECK-LABEL: and_eq:438; CHECK: # %bb.0:439; CHECK-NEXT: xor r3, r3, r4440; CHECK-NEXT: xor r4, r5, r6441; CHECK-NEXT: or r3, r3, r4442; CHECK-NEXT: cntlzw r3, r3443; CHECK-NEXT: srwi r3, r3, 5444; CHECK-NEXT: blr445 %cmp1 = icmp eq i16 %a, %b446 %cmp2 = icmp eq i16 %c, %d447 %and = and i1 %cmp1, %cmp2448 ret i1 %and449}450 451define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) {452; CHECK-LABEL: or_ne:453; CHECK: # %bb.0:454; CHECK-NEXT: xor r3, r3, r4455; CHECK-NEXT: xor r4, r5, r6456; CHECK-NEXT: or r3, r3, r4457; CHECK-NEXT: cntlzw r3, r3458; CHECK-NEXT: srwi r3, r3, 5459; CHECK-NEXT: xori r3, r3, 1460; CHECK-NEXT: blr461 %cmp1 = icmp ne i32 %a, %b462 %cmp2 = icmp ne i32 %c, %d463 %or = or i1 %cmp1, %cmp2464 ret i1 %or465}466 467; This should not be transformed because vector compares + bitwise logic are faster.468 469define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {470; CHECK-LABEL: and_eq_vec:471; CHECK: # %bb.0:472; CHECK-NEXT: vcmpequw v2, v2, v3473; CHECK-NEXT: vcmpequw v3, v4, v5474; CHECK-NEXT: xxland v2, v2, v3475; CHECK-NEXT: blr476 %cmp1 = icmp eq <4 x i32> %a, %b477 %cmp2 = icmp eq <4 x i32> %c, %d478 %and = and <4 x i1> %cmp1, %cmp2479 ret <4 x i1> %and480}481 482define i1 @or_icmps_const_1bit_diff(i64 %x) {483; CHECK-LABEL: or_icmps_const_1bit_diff:484; CHECK: # %bb.0:485; CHECK-NEXT: addi r3, r3, -13486; CHECK-NEXT: rldicl r3, r3, 61, 1487; CHECK-NEXT: rotldi r3, r3, 3488; CHECK-NEXT: cntlzd r3, r3489; CHECK-NEXT: rldicl r3, r3, 58, 63490; CHECK-NEXT: blr491 %a = icmp eq i64 %x, 17492 %b = icmp eq i64 %x, 13493 %r = or i1 %a, %b494 ret i1 %r495}496 497define i1 @and_icmps_const_1bit_diff(i32 %x) {498; CHECK-LABEL: and_icmps_const_1bit_diff:499; CHECK: # %bb.0:500; CHECK-NEXT: addi r3, r3, -4625501; CHECK-NEXT: rlwinm r3, r3, 0, 28, 26502; CHECK-NEXT: cntlzw r3, r3503; CHECK-NEXT: not r3, r3504; CHECK-NEXT: rlwinm r3, r3, 27, 31, 31505; CHECK-NEXT: blr506 %a = icmp ne i32 %x, 4625507 %b = icmp ne i32 %x, 4641508 %r = and i1 %a, %b509 ret i1 %r510}511 512