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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s3; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s4define <4 x i32> @test_signext_vector_inreg(<4 x i16> %n) {5; CHECK-P9-LABEL: test_signext_vector_inreg:6; CHECK-P9: # %bb.0: # %entry7; CHECK-P9-NEXT: vmrglh 2, 2, 28; CHECK-P9-NEXT: vextsh2w 2, 29; CHECK-P9-NEXT: blr10;11; CHECK-P8-LABEL: test_signext_vector_inreg:12; CHECK-P8: # %bb.0: # %entry13; CHECK-P8-NEXT: vspltisw 3, 814; CHECK-P8-NEXT: vmrglh 2, 2, 215; CHECK-P8-NEXT: vadduwm 3, 3, 316; CHECK-P8-NEXT: vslw 2, 2, 317; CHECK-P8-NEXT: vsraw 2, 2, 318; CHECK-P8-NEXT: blr19entry:20 %0 = sext <4 x i16> %n to <4 x i32>21 ret <4 x i32> %022}23