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1; RUN: llc -verify-machineinstrs < %s | FileCheck --check-prefix=P8 --check-prefix=CHECK %s2; RUN: llc -mcpu=pwr9 -verify-machineinstrs < %s | FileCheck --check-prefix=P9 --check-prefix=CHECK %s3target datalayout = "e-m:e-i64:64-n32:64"4target triple = "powerpc64le-unknown-linux-gnu"5 6; CHECK-LABEL: lshr:7; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 648; CHECK-DAG: addi [[R1:[0-9]+]], 5, -649; CHECK-DAG: srd [[R2:[0-9]+]], 3, 510; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]]11; CHECK-DAG: srd [[R4:[0-9]+]], 4, [[R1]]12; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]13; CHECK-DAG: or 3, [[R5]], [[R4]]14; CHECK-DAG: srd 4, 4, 515; CHECK: blr16define i128 @lshr(i128 %x, i128 %y) {17 %r = lshr i128 %x, %y18 ret i128 %r19}20; CHECK-LABEL: ashr:21; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 6422; CHECK-DAG: addi [[R1:[0-9]+]], 5, -6423; CHECK-DAG: srd [[R2:[0-9]+]], 3, 524; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]]25; CHECK-DAG: srad [[R4:[0-9]+]], 4, [[R1]]26; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]27; CHECK-DAG: cmpwi [[R1]], 128; CHECK-DAG: srad 4, 4, 529; CHECK-DAG: isellt 3, [[R5]], [[R4]]30; CHECK: blr31define i128 @ashr(i128 %x, i128 %y) {32 %r = ashr i128 %x, %y33 ret i128 %r34}35; CHECK-LABEL: shl:36; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 6437; CHECK-DAG: addi [[R1:[0-9]+]], 5, -6438; CHECK-DAG: sld [[R2:[0-9]+]], 4, 539; CHECK-DAG: srd [[R3:[0-9]+]], 3, [[R0]]40; CHECK-DAG: sld [[R4:[0-9]+]], 3, [[R1]]41; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]42; CHECK-DAG: or 4, [[R5]], [[R4]]43; CHECK-DAG: sld 3, 3, 544; CHECK: blr45define i128 @shl(i128 %x, i128 %y) {46 %r = shl i128 %x, %y47 ret i128 %r48}49 50; CHECK-LABEL: shl_v1i128:51; P8-NOT: {{\b}}vslo52; P8-NOT: {{\b}}vsl53; P9-DAG: vslo54; P9-DAG: vspltb55; P9: vsl56; P9-NOT: {{\b}}sld57; P9-NOT: {{\b}}srd58; CHECK: blr59define i128 @shl_v1i128(i128 %arg, i128 %amt) local_unnamed_addr #0 {60entry:61 %0 = insertelement <1 x i128> undef, i128 %arg, i32 062 %1 = insertelement <1 x i128> undef, i128 %amt, i32 063 %2 = shl <1 x i128> %0, %164 %retval = extractelement <1 x i128> %2, i32 065 ret i128 %retval66}67 68; CHECK-LABEL: lshr_v1i128:69; P8-NOT: {{\b}}vsro70; P8-NOT: {{\b}}vsr71; P9-DAG: vsro72; P9-DAG: vspltb73; P9: vsr74; P9-NOT: {{\b}}srd75; P9-NOT: {{\b}}sld76; CHECK: blr77define i128 @lshr_v1i128(i128 %arg, i128 %amt) local_unnamed_addr #0 {78entry:79 %0 = insertelement <1 x i128> undef, i128 %arg, i32 080 %1 = insertelement <1 x i128> undef, i128 %amt, i32 081 %2 = lshr <1 x i128> %0, %182 %retval = extractelement <1 x i128> %2, i32 083 ret i128 %retval84}85 86; Arithmetic shift right is not available as an operation on the vector registers.87; CHECK-LABEL: ashr_v1i128:88; CHECK-NOT: {{\b}}vsro89; CHECK-NOT: {{\b}}vsr90; CHECK: blr91define i128 @ashr_v1i128(i128 %arg, i128 %amt) local_unnamed_addr #0 {92entry:93 %0 = insertelement <1 x i128> undef, i128 %arg, i32 094 %1 = insertelement <1 x i128> undef, i128 %amt, i32 095 %2 = ashr <1 x i128> %0, %196 %retval = extractelement <1 x i128> %2, i32 097 ret i128 %retval98}99