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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3target triple = "powerpc64le-linux-gnu"4 5define i8 @test000(i8 %a, i8 %b) {6; CHECK-LABEL: test000:7; CHECK: # %bb.0:8; CHECK-NEXT: clrlwi 4, 4, 299; CHECK-NEXT: slw 3, 3, 410; CHECK-NEXT: blr11 %rem = and i8 %b, 712 %shl = shl i8 %a, %rem13 ret i8 %shl14}15 16define i16 @test001(i16 %a, i16 %b) {17; CHECK-LABEL: test001:18; CHECK: # %bb.0:19; CHECK-NEXT: clrlwi 4, 4, 2820; CHECK-NEXT: slw 3, 3, 421; CHECK-NEXT: blr22 %rem = and i16 %b, 1523 %shl = shl i16 %a, %rem24 ret i16 %shl25}26 27define i32 @test002(i32 %a, i32 %b) {28; CHECK-LABEL: test002:29; CHECK: # %bb.0:30; CHECK-NEXT: clrlwi 4, 4, 2731; CHECK-NEXT: slw 3, 3, 432; CHECK-NEXT: blr33 %rem = and i32 %b, 3134 %shl = shl i32 %a, %rem35 ret i32 %shl36}37 38define i64 @test003(i64 %a, i64 %b) {39; CHECK-LABEL: test003:40; CHECK: # %bb.0:41; CHECK-NEXT: clrlwi 4, 4, 2642; CHECK-NEXT: sld 3, 3, 443; CHECK-NEXT: blr44 %rem = and i64 %b, 6345 %shl = shl i64 %a, %rem46 ret i64 %shl47}48 49define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) {50; CHECK-LABEL: test010:51; CHECK: # %bb.0:52; CHECK-NEXT: vslb 2, 2, 353; CHECK-NEXT: blr54 %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>55 %shl = shl <16 x i8> %a, %rem56 ret <16 x i8> %shl57}58 59define <8 x i16> @test011(<8 x i16> %a, <8 x i16> %b) {60; CHECK-LABEL: test011:61; CHECK: # %bb.0:62; CHECK-NEXT: vslh 2, 2, 363; CHECK-NEXT: blr64 %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>65 %shl = shl <8 x i16> %a, %rem66 ret <8 x i16> %shl67}68 69define <4 x i32> @test012(<4 x i32> %a, <4 x i32> %b) {70; CHECK-LABEL: test012:71; CHECK: # %bb.0:72; CHECK-NEXT: vslw 2, 2, 373; CHECK-NEXT: blr74 %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>75 %shl = shl <4 x i32> %a, %rem76 ret <4 x i32> %shl77}78 79define <2 x i64> @test013(<2 x i64> %a, <2 x i64> %b) {80; CHECK-LABEL: test013:81; CHECK: # %bb.0:82; CHECK-NEXT: vsld 2, 2, 383; CHECK-NEXT: blr84 %rem = and <2 x i64> %b, <i64 63, i64 63>85 %shl = shl <2 x i64> %a, %rem86 ret <2 x i64> %shl87}88 89define i8 @test100(i8 %a, i8 %b) {90; CHECK-LABEL: test100:91; CHECK: # %bb.0:92; CHECK-NEXT: clrlwi 3, 3, 2493; CHECK-NEXT: clrlwi 4, 4, 2994; CHECK-NEXT: srw 3, 3, 495; CHECK-NEXT: blr96 %rem = and i8 %b, 797 %lshr = lshr i8 %a, %rem98 ret i8 %lshr99}100 101define i16 @test101(i16 %a, i16 %b) {102; CHECK-LABEL: test101:103; CHECK: # %bb.0:104; CHECK-NEXT: clrlwi 3, 3, 16105; CHECK-NEXT: clrlwi 4, 4, 28106; CHECK-NEXT: srw 3, 3, 4107; CHECK-NEXT: blr108 %rem = and i16 %b, 15109 %lshr = lshr i16 %a, %rem110 ret i16 %lshr111}112 113define i32 @test102(i32 %a, i32 %b) {114; CHECK-LABEL: test102:115; CHECK: # %bb.0:116; CHECK-NEXT: clrlwi 4, 4, 27117; CHECK-NEXT: srw 3, 3, 4118; CHECK-NEXT: blr119 %rem = and i32 %b, 31120 %lshr = lshr i32 %a, %rem121 ret i32 %lshr122}123 124define i64 @test103(i64 %a, i64 %b) {125; CHECK-LABEL: test103:126; CHECK: # %bb.0:127; CHECK-NEXT: clrlwi 4, 4, 26128; CHECK-NEXT: srd 3, 3, 4129; CHECK-NEXT: blr130 %rem = and i64 %b, 63131 %lshr = lshr i64 %a, %rem132 ret i64 %lshr133}134 135define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) {136; CHECK-LABEL: test110:137; CHECK: # %bb.0:138; CHECK-NEXT: vsrb 2, 2, 3139; CHECK-NEXT: blr140 %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>141 %lshr = lshr <16 x i8> %a, %rem142 ret <16 x i8> %lshr143}144 145define <8 x i16> @test111(<8 x i16> %a, <8 x i16> %b) {146; CHECK-LABEL: test111:147; CHECK: # %bb.0:148; CHECK-NEXT: vsrh 2, 2, 3149; CHECK-NEXT: blr150 %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>151 %lshr = lshr <8 x i16> %a, %rem152 ret <8 x i16> %lshr153}154 155define <4 x i32> @test112(<4 x i32> %a, <4 x i32> %b) {156; CHECK-LABEL: test112:157; CHECK: # %bb.0:158; CHECK-NEXT: vsrw 2, 2, 3159; CHECK-NEXT: blr160 %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>161 %lshr = lshr <4 x i32> %a, %rem162 ret <4 x i32> %lshr163}164 165define <2 x i64> @test113(<2 x i64> %a, <2 x i64> %b) {166; CHECK-LABEL: test113:167; CHECK: # %bb.0:168; CHECK-NEXT: vsrd 2, 2, 3169; CHECK-NEXT: blr170 %rem = and <2 x i64> %b, <i64 63, i64 63>171 %lshr = lshr <2 x i64> %a, %rem172 ret <2 x i64> %lshr173}174 175define i8 @test200(i8 %a, i8 %b) {176; CHECK-LABEL: test200:177; CHECK: # %bb.0:178; CHECK-NEXT: extsb 3, 3179; CHECK-NEXT: clrlwi 4, 4, 29180; CHECK-NEXT: sraw 3, 3, 4181; CHECK-NEXT: blr182 %rem = and i8 %b, 7183 %ashr = ashr i8 %a, %rem184 ret i8 %ashr185}186 187define i16 @test201(i16 %a, i16 %b) {188; CHECK-LABEL: test201:189; CHECK: # %bb.0:190; CHECK-NEXT: extsh 3, 3191; CHECK-NEXT: clrlwi 4, 4, 28192; CHECK-NEXT: sraw 3, 3, 4193; CHECK-NEXT: blr194 %rem = and i16 %b, 15195 %ashr = ashr i16 %a, %rem196 ret i16 %ashr197}198 199define i32 @test202(i32 %a, i32 %b) {200; CHECK-LABEL: test202:201; CHECK: # %bb.0:202; CHECK-NEXT: clrlwi 4, 4, 27203; CHECK-NEXT: sraw 3, 3, 4204; CHECK-NEXT: blr205 %rem = and i32 %b, 31206 %ashr = ashr i32 %a, %rem207 ret i32 %ashr208}209 210define i64 @test203(i64 %a, i64 %b) {211; CHECK-LABEL: test203:212; CHECK: # %bb.0:213; CHECK-NEXT: clrlwi 4, 4, 26214; CHECK-NEXT: srad 3, 3, 4215; CHECK-NEXT: blr216 %rem = and i64 %b, 63217 %ashr = ashr i64 %a, %rem218 ret i64 %ashr219}220 221define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) {222; CHECK-LABEL: test210:223; CHECK: # %bb.0:224; CHECK-NEXT: vsrab 2, 2, 3225; CHECK-NEXT: blr226 %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>227 %ashr = ashr <16 x i8> %a, %rem228 ret <16 x i8> %ashr229}230 231define <8 x i16> @test211(<8 x i16> %a, <8 x i16> %b) {232; CHECK-LABEL: test211:233; CHECK: # %bb.0:234; CHECK-NEXT: vsrah 2, 2, 3235; CHECK-NEXT: blr236 %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>237 %ashr = ashr <8 x i16> %a, %rem238 ret <8 x i16> %ashr239}240 241define <4 x i32> @test212(<4 x i32> %a, <4 x i32> %b) {242; CHECK-LABEL: test212:243; CHECK: # %bb.0:244; CHECK-NEXT: vsraw 2, 2, 3245; CHECK-NEXT: blr246 %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>247 %ashr = ashr <4 x i32> %a, %rem248 ret <4 x i32> %ashr249}250 251define <2 x i64> @test213(<2 x i64> %a, <2 x i64> %b) {252; CHECK-LABEL: test213:253; CHECK: # %bb.0:254; CHECK-NEXT: vsrad 2, 2, 3255; CHECK-NEXT: blr256 %rem = and <2 x i64> %b, <i64 63, i64 63>257 %ashr = ashr <2 x i64> %a, %rem258 ret <2 x i64> %ashr259}260