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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s3 4; If positive...5 6define i32 @zext_ifpos(i32 %x) {7; CHECK-LABEL: zext_ifpos:8; CHECK: # %bb.0:9; CHECK-NEXT: rlwinm 3, 3, 1, 31, 3110; CHECK-NEXT: xori 3, 3, 111; CHECK-NEXT: blr12 %c = icmp sgt i32 %x, -113 %e = zext i1 %c to i3214 ret i32 %e15}16 17define i32 @add_zext_ifpos(i32 %x) {18; CHECK-LABEL: add_zext_ifpos:19; CHECK: # %bb.0:20; CHECK-NEXT: srawi 3, 3, 3121; CHECK-NEXT: addi 3, 3, 4222; CHECK-NEXT: blr23 %c = icmp sgt i32 %x, -124 %e = zext i1 %c to i3225 %r = add i32 %e, 4126 ret i32 %r27}28 29define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {30; CHECK-LABEL: add_zext_ifpos_vec_splat:31; CHECK: # %bb.0:32; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha33; CHECK-NEXT: xxleqv 35, 35, 3534; CHECK-NEXT: vcmpgtsw 2, 2, 335; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l36; CHECK-NEXT: lxvd2x 35, 0, 337; CHECK-NEXT: vsubuwm 2, 3, 238; CHECK-NEXT: blr39 %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>40 %e = zext <4 x i1> %c to <4 x i32>41 %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>42 ret <4 x i32> %r43}44 45define i32 @sel_ifpos_tval_bigger(i32 %x) {46; CHECK-LABEL: sel_ifpos_tval_bigger:47; CHECK: # %bb.0:48; CHECK-NEXT: rlwinm 3, 3, 1, 31, 3149; CHECK-NEXT: xori 3, 3, 150; CHECK-NEXT: addi 3, 3, 4151; CHECK-NEXT: blr52 %c = icmp sgt i32 %x, -153 %r = select i1 %c, i32 42, i32 4154 ret i32 %r55}56 57define i32 @sext_ifpos(i32 %x) {58; CHECK-LABEL: sext_ifpos:59; CHECK: # %bb.0:60; CHECK-NEXT: not 3, 361; CHECK-NEXT: srawi 3, 3, 3162; CHECK-NEXT: blr63 %c = icmp sgt i32 %x, -164 %e = sext i1 %c to i3265 ret i32 %e66}67 68define i32 @add_sext_ifpos(i32 %x) {69; CHECK-LABEL: add_sext_ifpos:70; CHECK: # %bb.0:71; CHECK-NEXT: srwi 3, 3, 3172; CHECK-NEXT: addi 3, 3, 4173; CHECK-NEXT: blr74 %c = icmp sgt i32 %x, -175 %e = sext i1 %c to i3276 %r = add i32 %e, 4277 ret i32 %r78}79 80define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {81; CHECK-LABEL: add_sext_ifpos_vec_splat:82; CHECK: # %bb.0:83; CHECK-NEXT: addis 3, 2, .LCPI6_0@toc@ha84; CHECK-NEXT: xxleqv 35, 35, 3585; CHECK-NEXT: vcmpgtsw 2, 2, 386; CHECK-NEXT: addi 3, 3, .LCPI6_0@toc@l87; CHECK-NEXT: lxvd2x 35, 0, 388; CHECK-NEXT: vadduwm 2, 2, 389; CHECK-NEXT: blr90 %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>91 %e = sext <4 x i1> %c to <4 x i32>92 %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>93 ret <4 x i32> %r94}95 96define i32 @sel_ifpos_fval_bigger(i32 %x) {97; CHECK-LABEL: sel_ifpos_fval_bigger:98; CHECK: # %bb.0:99; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31100; CHECK-NEXT: xori 3, 3, 1101; CHECK-NEXT: subfic 3, 3, 42102; CHECK-NEXT: blr103 %c = icmp sgt i32 %x, -1104 %r = select i1 %c, i32 41, i32 42105 ret i32 %r106}107 108; If negative...109 110define i32 @zext_ifneg(i32 %x) {111; CHECK-LABEL: zext_ifneg:112; CHECK: # %bb.0:113; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31114; CHECK-NEXT: blr115 %c = icmp slt i32 %x, 0116 %r = zext i1 %c to i32117 ret i32 %r118}119 120define i32 @add_zext_ifneg(i32 %x) {121; CHECK-LABEL: add_zext_ifneg:122; CHECK: # %bb.0:123; CHECK-NEXT: srwi 3, 3, 31124; CHECK-NEXT: addi 3, 3, 41125; CHECK-NEXT: blr126 %c = icmp slt i32 %x, 0127 %e = zext i1 %c to i32128 %r = add i32 %e, 41129 ret i32 %r130}131 132define i32 @sel_ifneg_tval_bigger(i32 %x) {133; CHECK-LABEL: sel_ifneg_tval_bigger:134; CHECK: # %bb.0:135; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31136; CHECK-NEXT: addi 3, 3, 41137; CHECK-NEXT: blr138 %c = icmp slt i32 %x, 0139 %r = select i1 %c, i32 42, i32 41140 ret i32 %r141}142 143define i32 @sext_ifneg(i32 %x) {144; CHECK-LABEL: sext_ifneg:145; CHECK: # %bb.0:146; CHECK-NEXT: srawi 3, 3, 31147; CHECK-NEXT: blr148 %c = icmp slt i32 %x, 0149 %r = sext i1 %c to i32150 ret i32 %r151}152 153define i32 @add_sext_ifneg(i32 %x) {154; CHECK-LABEL: add_sext_ifneg:155; CHECK: # %bb.0:156; CHECK-NEXT: srawi 3, 3, 31157; CHECK-NEXT: addi 3, 3, 42158; CHECK-NEXT: blr159 %c = icmp slt i32 %x, 0160 %e = sext i1 %c to i32161 %r = add i32 %e, 42162 ret i32 %r163}164 165define i32 @sel_ifneg_fval_bigger(i32 %x) {166; CHECK-LABEL: sel_ifneg_fval_bigger:167; CHECK: # %bb.0:168; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31169; CHECK-NEXT: subfic 3, 3, 42170; CHECK-NEXT: blr171 %c = icmp slt i32 %x, 0172 %r = select i1 %c, i32 41, i32 42173 ret i32 %r174}175 176define i32 @add_lshr_not(i32 %x) {177; CHECK-LABEL: add_lshr_not:178; CHECK: # %bb.0:179; CHECK-NEXT: srawi 3, 3, 31180; CHECK-NEXT: addi 3, 3, 42181; CHECK-NEXT: blr182 %not = xor i32 %x, -1183 %sh = lshr i32 %not, 31184 %r = add i32 %sh, 41185 ret i32 %r186}187 188define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {189; CHECK-LABEL: add_lshr_not_vec_splat:190; CHECK: # %bb.0:191; CHECK-NEXT: addis 3, 2, .LCPI15_0@toc@ha192; CHECK-NEXT: xxleqv 35, 35, 35193; CHECK-NEXT: vsraw 2, 2, 3194; CHECK-NEXT: addi 3, 3, .LCPI15_0@toc@l195; CHECK-NEXT: lxvd2x 35, 0, 3196; CHECK-NEXT: vadduwm 2, 2, 3197; CHECK-NEXT: blr198 %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>199 %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>200 %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>201 ret <4 x i32> %r202}203 204define i32 @sub_lshr_not(i32 %x) {205; CHECK-LABEL: sub_lshr_not:206; CHECK: # %bb.0:207; CHECK-NEXT: srwi 3, 3, 31208; CHECK-NEXT: ori 3, 3, 42209; CHECK-NEXT: blr210 %not = xor i32 %x, -1211 %sh = lshr i32 %not, 31212 %r = sub i32 43, %sh213 ret i32 %r214}215 216define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {217; CHECK-LABEL: sub_lshr_not_vec_splat:218; CHECK: # %bb.0:219; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha220; CHECK-NEXT: xxleqv 35, 35, 35221; CHECK-NEXT: vsrw 2, 2, 3222; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l223; CHECK-NEXT: lxvd2x 35, 0, 3224; CHECK-NEXT: vadduwm 2, 2, 3225; CHECK-NEXT: blr226 %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>227 %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>228 %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e229 ret <4 x i32> %r230}231 232define i32 @sub_lshr(i32 %x, i32 %y) {233; CHECK-LABEL: sub_lshr:234; CHECK: # %bb.0:235; CHECK-NEXT: srawi 3, 3, 31236; CHECK-NEXT: add 3, 4, 3237; CHECK-NEXT: blr238 %sh = lshr i32 %x, 31239 %r = sub i32 %y, %sh240 ret i32 %r241}242 243define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {244; CHECK-LABEL: sub_lshr_vec:245; CHECK: # %bb.0:246; CHECK-NEXT: xxleqv 36, 36, 36247; CHECK-NEXT: vsraw 2, 2, 4248; CHECK-NEXT: vadduwm 2, 3, 2249; CHECK-NEXT: blr250 %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>251 %r = sub <4 x i32> %y, %sh252 ret <4 x i32> %r253}254 255define i32 @sub_const_op_lshr(i32 %x) {256; CHECK-LABEL: sub_const_op_lshr:257; CHECK: # %bb.0:258; CHECK-NEXT: srawi 3, 3, 31259; CHECK-NEXT: addi 3, 3, 43260; CHECK-NEXT: blr261 %sh = lshr i32 %x, 31262 %r = sub i32 43, %sh263 ret i32 %r264}265 266define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {267; CHECK-LABEL: sub_const_op_lshr_vec:268; CHECK: # %bb.0:269; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha270; CHECK-NEXT: xxleqv 35, 35, 35271; CHECK-NEXT: vsraw 2, 2, 3272; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l273; CHECK-NEXT: lxvd2x 35, 0, 3274; CHECK-NEXT: vadduwm 2, 2, 3275; CHECK-NEXT: blr276 %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>277 %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh278 ret <4 x i32> %r279}280 281