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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\3; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s4 5; Test that the pipeliner schedules the store instructions correctly. Since6; there is a dependence between the store, they cannot be scheduled further than7; MII cycles/instructions apart. That is, the first store cannot occur multiple8; times before the second ctore in the schedule.9define dso_local void @comp_method(ptr noalias nocapture noundef readonly %0, ptr nocapture noundef writeonly %1, ptr nocapture noundef writeonly %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i64 %v1) local_unnamed_addr {10; CHECK-LABEL: comp_method:11; CHECK: # %bb.0:12; CHECK-NEXT: extsw 7, 813; CHECK-NEXT: extsw 8, 914; CHECK-NEXT: clrldi 9, 6, 3215; CHECK-NEXT: addi 6, 3, -116; CHECK-NEXT: mtctr 917; CHECK-NEXT: li 11, 018; CHECK-NEXT: sradi 12, 11, 219; CHECK-NEXT: add 5, 5, 820; CHECK-NEXT: li 8, 221; CHECK-NEXT: li 3, 822; CHECK-NEXT: addi 11, 7, 023; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill24; CHECK-NEXT: lbzu 9, 1(6)25; CHECK-NEXT: add 12, 12, 1026; CHECK-NEXT: extsb 9, 927; CHECK-NEXT: stbx 8, 4, 928; CHECK-NEXT: add 9, 9, 1229; CHECK-NEXT: bdz .LBB0_230; CHECK-NEXT: .p2align 431; CHECK-NEXT: .LBB0_1:32; CHECK-NEXT: lbzu 0, 1(6)33; CHECK-NEXT: sradi 12, 11, 234; CHECK-NEXT: add 11, 11, 735; CHECK-NEXT: add 12, 12, 1036; CHECK-NEXT: sldi 30, 9, 237; CHECK-NEXT: add 9, 9, 3038; CHECK-NEXT: extsb 0, 039; CHECK-NEXT: stbx 3, 5, 940; CHECK-NEXT: add 9, 0, 1241; CHECK-NEXT: stbx 8, 4, 042; CHECK-NEXT: bdnz .LBB0_143; CHECK-NEXT: .LBB0_2:44; CHECK-NEXT: sldi 4, 9, 245; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload46; CHECK-NEXT: add 4, 9, 447; CHECK-NEXT: stbx 3, 5, 448; CHECK-NEXT: blr49 %8 = icmp sgt i32 %3, 6450 tail call void @llvm.assume(i1 %8)51 %9 = and i32 %3, 152 %10 = icmp eq i32 %9, 053 tail call void @llvm.assume(i1 %10)54 %11 = sext i32 %5 to i6455 %12 = sext i32 %6 to i6456 %13 = zext nneg i32 %3 to i6457 %14 = getelementptr i8, ptr %2, i64 %1258 br label %1659 6015:61 ret void62 6316:64 %17 = phi i64 [ 0, %7 ], [ %24, %16 ]65 %18 = getelementptr inbounds i8, ptr %0, i64 %1766 %19 = load i8, ptr %18, align 167 %20 = sext i8 %19 to i6468 %21 = getelementptr inbounds i8, ptr %1, i64 %2069 store i8 2, ptr %21, align 170 %22 = mul nsw i64 %17, %1171 %a1 = ashr i64 %22, 272 %a2 = add i64 %a1, %v173 %a3 = add i64 %20, %a274 %a4 = mul nsw i64 %a3, 575 %23 = getelementptr i8, ptr %14, i64 %a476 store i8 8, ptr %23, align 177 %24 = add nuw nsw i64 %17, 178 %25 = icmp eq i64 %24, %1379 br i1 %25, label %15, label %1680}81 82declare void @llvm.assume(i1 noundef) #183 84attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }85