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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \3; RUN: -mattr=+spe | FileCheck %s -check-prefixes=CHECK,SPE4; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \5; RUN: -mattr=+efpu2 | FileCheck %s -check-prefixes=CHECK,EFPU26 7; single tests (identical for -mattr=+spe and -mattr=+efpu2)8 9declare float @llvm.fabs.float(float)10define float @test_float_abs(float %a) #0 {11; CHECK-LABEL: test_float_abs:12; CHECK: # %bb.0: # %entry13; CHECK-NEXT: efsabs 3, 314; CHECK-NEXT: blr15 entry:16 %0 = tail call float @llvm.fabs.float(float %a)17 ret float %018}19 20define float @test_fnabs(float %a) #0 {21; CHECK-LABEL: test_fnabs:22; CHECK: # %bb.0: # %entry23; CHECK-NEXT: efsnabs 3, 324; CHECK-NEXT: blr25 entry:26 %0 = tail call float @llvm.fabs.float(float %a)27 %sub = fsub float -0.000000e+00, %028 ret float %sub29}30 31define float @test_fdiv(float %a, float %b) #0 {32; CHECK-LABEL: test_fdiv:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: efsdiv 3, 3, 435; CHECK-NEXT: blr36entry:37 %v = fdiv float %a, %b38 ret float %v39 40}41 42define float @test_fmul(float %a, float %b) #0 {43; CHECK-LABEL: test_fmul:44; CHECK: # %bb.0: # %entry45; CHECK-NEXT: efsmul 3, 3, 446; CHECK-NEXT: blr47 entry:48 %v = fmul float %a, %b49 ret float %v50}51 52define float @test_fadd(float %a, float %b) #0 {53; CHECK-LABEL: test_fadd:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: efsadd 3, 3, 456; CHECK-NEXT: blr57 entry:58 %v = fadd float %a, %b59 ret float %v60}61 62define float @test_fsub(float %a, float %b) #0 {63; CHECK-LABEL: test_fsub:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: efssub 3, 3, 466; CHECK-NEXT: blr67 entry:68 %v = fsub float %a, %b69 ret float %v70}71 72define float @test_fneg(float %a) #0 {73; CHECK-LABEL: test_fneg:74; CHECK: # %bb.0: # %entry75; CHECK-NEXT: efsneg 3, 376; CHECK-NEXT: blr77 entry:78 %v = fsub float -0.0, %a79 ret float %v80}81 82define i32 @test_fcmpgt(float %a, float %b) #0 {83; CHECK-LABEL: test_fcmpgt:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: stwu 1, -16(1)86; CHECK-NEXT: efscmpgt 0, 3, 487; CHECK-NEXT: ble 0, .LBB7_288; CHECK-NEXT: # %bb.1: # %tr89; CHECK-NEXT: li 3, 190; CHECK-NEXT: b .LBB7_391; CHECK-NEXT: .LBB7_2: # %fa92; CHECK-NEXT: li 3, 093; CHECK-NEXT: .LBB7_3: # %ret94; CHECK-NEXT: stw 3, 12(1)95; CHECK-NEXT: lwz 3, 12(1)96; CHECK-NEXT: addi 1, 1, 1697; CHECK-NEXT: blr98 entry:99 %r = alloca i32, align 4100 %c = fcmp ogt float %a, %b101 br i1 %c, label %tr, label %fa102tr:103 store i32 1, ptr %r, align 4104 br label %ret105fa:106 store i32 0, ptr %r, align 4107 br label %ret108ret:109 %0 = load i32, ptr %r, align 4110 ret i32 %0111}112 113define i32 @test_fcmpugt(float %a, float %b) #0 {114; CHECK-LABEL: test_fcmpugt:115; CHECK: # %bb.0: # %entry116; CHECK-NEXT: stwu 1, -16(1)117; CHECK-NEXT: efscmpeq 0, 4, 4118; CHECK-NEXT: bc 4, 1, .LBB8_4119; CHECK-NEXT: # %bb.1: # %entry120; CHECK-NEXT: efscmpeq 0, 3, 3121; CHECK-NEXT: bc 4, 1, .LBB8_4122; CHECK-NEXT: # %bb.2: # %entry123; CHECK-NEXT: efscmpgt 0, 3, 4124; CHECK-NEXT: bc 12, 1, .LBB8_4125; CHECK-NEXT: # %bb.3: # %fa126; CHECK-NEXT: li 3, 0127; CHECK-NEXT: b .LBB8_5128; CHECK-NEXT: .LBB8_4: # %tr129; CHECK-NEXT: li 3, 1130; CHECK-NEXT: .LBB8_5: # %ret131; CHECK-NEXT: stw 3, 12(1)132; CHECK-NEXT: lwz 3, 12(1)133; CHECK-NEXT: addi 1, 1, 16134; CHECK-NEXT: blr135 entry:136 %r = alloca i32, align 4137 %c = fcmp ugt float %a, %b138 br i1 %c, label %tr, label %fa139tr:140 store i32 1, ptr %r, align 4141 br label %ret142fa:143 store i32 0, ptr %r, align 4144 br label %ret145ret:146 %0 = load i32, ptr %r, align 4147 ret i32 %0148}149 150define i32 @test_fcmple(float %a, float %b) #0 {151; CHECK-LABEL: test_fcmple:152; CHECK: # %bb.0: # %entry153; CHECK-NEXT: stwu 1, -16(1)154; CHECK-NEXT: efscmpeq 0, 3, 3155; CHECK-NEXT: bc 4, 1, .LBB9_4156; CHECK-NEXT: # %bb.1: # %entry157; CHECK-NEXT: efscmpeq 0, 4, 4158; CHECK-NEXT: bc 4, 1, .LBB9_4159; CHECK-NEXT: # %bb.2: # %entry160; CHECK-NEXT: efscmpgt 0, 3, 4161; CHECK-NEXT: bc 12, 1, .LBB9_4162; CHECK-NEXT: # %bb.3: # %tr163; CHECK-NEXT: li 3, 1164; CHECK-NEXT: b .LBB9_5165; CHECK-NEXT: .LBB9_4: # %fa166; CHECK-NEXT: li 3, 0167; CHECK-NEXT: .LBB9_5: # %ret168; CHECK-NEXT: stw 3, 12(1)169; CHECK-NEXT: lwz 3, 12(1)170; CHECK-NEXT: addi 1, 1, 16171; CHECK-NEXT: blr172 entry:173 %r = alloca i32, align 4174 %c = fcmp ole float %a, %b175 br i1 %c, label %tr, label %fa176tr:177 store i32 1, ptr %r, align 4178 br label %ret179fa:180 store i32 0, ptr %r, align 4181 br label %ret182ret:183 %0 = load i32, ptr %r, align 4184 ret i32 %0185}186 187define i32 @test_fcmpule(float %a, float %b) #0 {188; CHECK-LABEL: test_fcmpule:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: stwu 1, -16(1)191; CHECK-NEXT: efscmpgt 0, 3, 4192; CHECK-NEXT: bgt 0, .LBB10_2193; CHECK-NEXT: # %bb.1: # %tr194; CHECK-NEXT: li 3, 1195; CHECK-NEXT: b .LBB10_3196; CHECK-NEXT: .LBB10_2: # %fa197; CHECK-NEXT: li 3, 0198; CHECK-NEXT: .LBB10_3: # %ret199; CHECK-NEXT: stw 3, 12(1)200; CHECK-NEXT: lwz 3, 12(1)201; CHECK-NEXT: addi 1, 1, 16202; CHECK-NEXT: blr203 entry:204 %r = alloca i32, align 4205 %c = fcmp ule float %a, %b206 br i1 %c, label %tr, label %fa207tr:208 store i32 1, ptr %r, align 4209 br label %ret210fa:211 store i32 0, ptr %r, align 4212 br label %ret213ret:214 %0 = load i32, ptr %r, align 4215 ret i32 %0216}217 218; The type of comparison found in C's if (x == y)219define i32 @test_fcmpeq(float %a, float %b) #0 {220; CHECK-LABEL: test_fcmpeq:221; CHECK: # %bb.0: # %entry222; CHECK-NEXT: stwu 1, -16(1)223; CHECK-NEXT: efscmpeq 0, 3, 4224; CHECK-NEXT: ble 0, .LBB11_2225; CHECK-NEXT: # %bb.1: # %tr226; CHECK-NEXT: li 3, 1227; CHECK-NEXT: b .LBB11_3228; CHECK-NEXT: .LBB11_2: # %fa229; CHECK-NEXT: li 3, 0230; CHECK-NEXT: .LBB11_3: # %ret231; CHECK-NEXT: stw 3, 12(1)232; CHECK-NEXT: lwz 3, 12(1)233; CHECK-NEXT: addi 1, 1, 16234; CHECK-NEXT: blr235 entry:236 %r = alloca i32, align 4237 %c = fcmp oeq float %a, %b238 br i1 %c, label %tr, label %fa239tr:240 store i32 1, ptr %r, align 4241 br label %ret242fa:243 store i32 0, ptr %r, align 4244 br label %ret245ret:246 %0 = load i32, ptr %r, align 4247 ret i32 %0248}249 250; (un)ordered tests are expanded to une and oeq so verify251define i1 @test_fcmpuno(float %a, float %b) #0 {252; CHECK-LABEL: test_fcmpuno:253; CHECK: # %bb.0: # %entry254; CHECK-NEXT: efscmpeq 0, 3, 3255; CHECK-NEXT: li 3, 0256; CHECK-NEXT: bc 4, 1, .LBB12_2257; CHECK-NEXT: # %bb.1: # %entry258; CHECK-NEXT: efscmpeq 0, 4, 4259; CHECK-NEXT: bclr 12, 1, 0260; CHECK-NEXT: .LBB12_2: # %entry261; CHECK-NEXT: li 3, 1262; CHECK-NEXT: blr263 entry:264 %r = fcmp uno float %a, %b265 ret i1 %r266}267 268define i1 @test_fcmpord(float %a, float %b) #0 {269; CHECK-LABEL: test_fcmpord:270; CHECK: # %bb.0: # %entry271; CHECK-NEXT: mr 5, 3272; CHECK-NEXT: efscmpeq 0, 4, 4273; CHECK-NEXT: li 3, 0274; CHECK-NEXT: bclr 4, 1, 0275; CHECK-NEXT: # %bb.1: # %entry276; CHECK-NEXT: efscmpeq 0, 5, 5277; CHECK-NEXT: bclr 4, 1, 0278; CHECK-NEXT: # %bb.2: # %entry279; CHECK-NEXT: li 3, 1280; CHECK-NEXT: blr281 entry:282 %r = fcmp ord float %a, %b283 ret i1 %r284}285 286define i1 @test_fcmpueq(float %a, float %b) #0 {287; CHECK-LABEL: test_fcmpueq:288; CHECK: # %bb.0: # %entry289; CHECK-NEXT: mr 5, 3290; CHECK-NEXT: efscmpgt 0, 3, 4291; CHECK-NEXT: li 3, 0292; CHECK-NEXT: bclr 12, 1, 0293; CHECK-NEXT: # %bb.1: # %entry294; CHECK-NEXT: efscmplt 0, 5, 4295; CHECK-NEXT: bclr 12, 1, 0296; CHECK-NEXT: # %bb.2: # %entry297; CHECK-NEXT: li 3, 1298; CHECK-NEXT: blr299 entry:300 %r = fcmp ueq float %a, %b301 ret i1 %r302}303 304define i1 @test_fcmpne(float %a, float %b) #0 {305; CHECK-LABEL: test_fcmpne:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: mr 5, 3308; CHECK-NEXT: efscmplt 0, 3, 4309; CHECK-NEXT: li 3, 0310; CHECK-NEXT: bc 12, 1, .LBB15_2311; CHECK-NEXT: # %bb.1: # %entry312; CHECK-NEXT: efscmpgt 0, 5, 4313; CHECK-NEXT: bclr 4, 1, 0314; CHECK-NEXT: .LBB15_2: # %entry315; CHECK-NEXT: li 3, 1316; CHECK-NEXT: blr317 entry:318 %r = fcmp one float %a, %b319 ret i1 %r320}321 322define i32 @test_fcmpune(float %a, float %b) #0 {323; CHECK-LABEL: test_fcmpune:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: stwu 1, -16(1)326; CHECK-NEXT: efscmpeq 0, 3, 4327; CHECK-NEXT: bgt 0, .LBB16_2328; CHECK-NEXT: # %bb.1: # %tr329; CHECK-NEXT: li 3, 1330; CHECK-NEXT: b .LBB16_3331; CHECK-NEXT: .LBB16_2: # %fa332; CHECK-NEXT: li 3, 0333; CHECK-NEXT: .LBB16_3: # %ret334; CHECK-NEXT: stw 3, 12(1)335; CHECK-NEXT: lwz 3, 12(1)336; CHECK-NEXT: addi 1, 1, 16337; CHECK-NEXT: blr338 entry:339 %r = alloca i32, align 4340 %c = fcmp une float %a, %b341 br i1 %c, label %tr, label %fa342tr:343 store i32 1, ptr %r, align 4344 br label %ret345fa:346 store i32 0, ptr %r, align 4347 br label %ret348ret:349 %0 = load i32, ptr %r, align 4350 ret i32 %0351}352 353define i32 @test_fcmplt(float %a, float %b) #0 {354; CHECK-LABEL: test_fcmplt:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: stwu 1, -16(1)357; CHECK-NEXT: efscmplt 0, 3, 4358; CHECK-NEXT: ble 0, .LBB17_2359; CHECK-NEXT: # %bb.1: # %tr360; CHECK-NEXT: li 3, 1361; CHECK-NEXT: b .LBB17_3362; CHECK-NEXT: .LBB17_2: # %fa363; CHECK-NEXT: li 3, 0364; CHECK-NEXT: .LBB17_3: # %ret365; CHECK-NEXT: stw 3, 12(1)366; CHECK-NEXT: lwz 3, 12(1)367; CHECK-NEXT: addi 1, 1, 16368; CHECK-NEXT: blr369 entry:370 %r = alloca i32, align 4371 %c = fcmp olt float %a, %b372 br i1 %c, label %tr, label %fa373tr:374 store i32 1, ptr %r, align 4375 br label %ret376fa:377 store i32 0, ptr %r, align 4378 br label %ret379ret:380 %0 = load i32, ptr %r, align 4381 ret i32 %0382}383 384define i1 @test_fcmpult(float %a, float %b) #0 {385; CHECK-LABEL: test_fcmpult:386; CHECK: # %bb.0: # %entry387; CHECK-NEXT: mr 5, 3388; CHECK-NEXT: efscmpeq 0, 3, 3389; CHECK-NEXT: li 3, 0390; CHECK-NEXT: bc 4, 1, .LBB18_3391; CHECK-NEXT: # %bb.1: # %entry392; CHECK-NEXT: efscmpeq 0, 4, 4393; CHECK-NEXT: bc 4, 1, .LBB18_3394; CHECK-NEXT: # %bb.2: # %entry395; CHECK-NEXT: efscmplt 0, 5, 4396; CHECK-NEXT: bclr 4, 1, 0397; CHECK-NEXT: .LBB18_3: # %entry398; CHECK-NEXT: li 3, 1399; CHECK-NEXT: blr400 entry:401 %r = fcmp ult float %a, %b402 ret i1 %r403}404 405define i32 @test_fcmpge(float %a, float %b) #0 {406; CHECK-LABEL: test_fcmpge:407; CHECK: # %bb.0: # %entry408; CHECK-NEXT: stwu 1, -16(1)409; CHECK-NEXT: efscmpeq 0, 3, 3410; CHECK-NEXT: bc 4, 1, .LBB19_4411; CHECK-NEXT: # %bb.1: # %entry412; CHECK-NEXT: efscmpeq 0, 4, 4413; CHECK-NEXT: bc 4, 1, .LBB19_4414; CHECK-NEXT: # %bb.2: # %entry415; CHECK-NEXT: efscmplt 0, 3, 4416; CHECK-NEXT: bc 12, 1, .LBB19_4417; CHECK-NEXT: # %bb.3: # %tr418; CHECK-NEXT: li 3, 1419; CHECK-NEXT: b .LBB19_5420; CHECK-NEXT: .LBB19_4: # %fa421; CHECK-NEXT: li 3, 0422; CHECK-NEXT: .LBB19_5: # %ret423; CHECK-NEXT: stw 3, 12(1)424; CHECK-NEXT: lwz 3, 12(1)425; CHECK-NEXT: addi 1, 1, 16426; CHECK-NEXT: blr427 entry:428 %r = alloca i32, align 4429 %c = fcmp oge float %a, %b430 br i1 %c, label %tr, label %fa431tr:432 store i32 1, ptr %r, align 4433 br label %ret434fa:435 store i32 0, ptr %r, align 4436 br label %ret437ret:438 %0 = load i32, ptr %r, align 4439 ret i32 %0440}441 442define i32 @test_fcmpuge(float %a, float %b) #0 {443; CHECK-LABEL: test_fcmpuge:444; CHECK: # %bb.0: # %entry445; CHECK-NEXT: stwu 1, -16(1)446; CHECK-NEXT: efscmplt 0, 3, 4447; CHECK-NEXT: bgt 0, .LBB20_2448; CHECK-NEXT: # %bb.1: # %tr449; CHECK-NEXT: li 3, 1450; CHECK-NEXT: b .LBB20_3451; CHECK-NEXT: .LBB20_2: # %fa452; CHECK-NEXT: li 3, 0453; CHECK-NEXT: .LBB20_3: # %ret454; CHECK-NEXT: stw 3, 12(1)455; CHECK-NEXT: lwz 3, 12(1)456; CHECK-NEXT: addi 1, 1, 16457; CHECK-NEXT: blr458 entry:459 %r = alloca i32, align 4460 %c = fcmp uge float %a, %b461 br i1 %c, label %tr, label %fa462tr:463 store i32 1, ptr %r, align 4464 br label %ret465fa:466 store i32 0, ptr %r, align 4467 br label %ret468ret:469 %0 = load i32, ptr %r, align 4470 ret i32 %0471}472 473 474define i32 @test_ftoui(float %a) #0 {475; CHECK-LABEL: test_ftoui:476; CHECK: # %bb.0:477; CHECK-NEXT: efsctuiz 3, 3478; CHECK-NEXT: blr479 %v = fptoui float %a to i32480 ret i32 %v481}482 483define i32 @test_ftosi(float %a) #0 {484; CHECK-LABEL: test_ftosi:485; CHECK: # %bb.0:486; CHECK-NEXT: efsctsiz 3, 3487; CHECK-NEXT: blr488 %v = fptosi float %a to i32489 ret i32 %v490}491 492define float @test_ffromui(i32 %a) #0 {493; CHECK-LABEL: test_ffromui:494; CHECK: # %bb.0:495; CHECK-NEXT: efscfui 3, 3496; CHECK-NEXT: blr497 %v = uitofp i32 %a to float498 ret float %v499}500 501define float @test_ffromsi(i32 %a) #0 {502; CHECK-LABEL: test_ffromsi:503; CHECK: # %bb.0:504; CHECK-NEXT: efscfsi 3, 3505; CHECK-NEXT: blr506 %v = sitofp i32 %a to float507 ret float %v508}509 510define i32 @test_fasmconst(float %x) #0 {511; CHECK-LABEL: test_fasmconst:512; CHECK: # %bb.0: # %entry513; CHECK-NEXT: stwu 1, -32(1)514; CHECK-NEXT: stw 3, 20(1)515; CHECK-NEXT: stw 3, 24(1)516; CHECK-NEXT: lwz 3, 20(1)517; CHECK-NEXT: #APP518; CHECK-NEXT: efsctsi 3, 3519; CHECK-NEXT: #NO_APP520; CHECK-NEXT: addi 1, 1, 32521; CHECK-NEXT: blr522entry:523 %x.addr = alloca float, align 8524 store float %x, ptr %x.addr, align 8525 %0 = load float, ptr %x.addr, align 8526 %1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0)527 ret i32 %1528; Check that it's not loading a double529}530attributes #0 = { nounwind }531 532; Double tests533; results depend on -mattr=+spe or -mattr=+efpu2534 535define float @test_dtos(double %a) #0 {536; SPE-LABEL: test_dtos:537; SPE: # %bb.0: # %entry538; SPE-NEXT: evmergelo 3, 3, 4539; SPE-NEXT: efscfd 3, 3540; SPE-NEXT: blr541;542; EFPU2-LABEL: test_dtos:543; EFPU2: # %bb.0: # %entry544; EFPU2-NEXT: mflr 0545; EFPU2-NEXT: stwu 1, -16(1)546; EFPU2-NEXT: stw 0, 20(1)547; EFPU2-NEXT: bl __truncdfsf2548; EFPU2-NEXT: lwz 0, 20(1)549; EFPU2-NEXT: addi 1, 1, 16550; EFPU2-NEXT: mtlr 0551; EFPU2-NEXT: blr552 entry:553 %v = fptrunc double %a to float554 ret float %v555}556 557define void @test_double_abs(ptr %aa) #0 {558; SPE-LABEL: test_double_abs:559; SPE: # %bb.0: # %entry560; SPE-NEXT: evldd 4, 0(3)561; SPE-NEXT: efdabs 4, 4562; SPE-NEXT: evstdd 4, 0(3)563; SPE-NEXT: blr564;565; EFPU2-LABEL: test_double_abs:566; EFPU2: # %bb.0: # %entry567; EFPU2-NEXT: lwz 4, 0(3)568; EFPU2-NEXT: clrlwi 4, 4, 1569; EFPU2-NEXT: stw 4, 0(3)570; EFPU2-NEXT: blr571 entry:572 %0 = load double, ptr %aa573 %1 = tail call double @llvm.fabs.f64(double %0) #2574 store double %1, ptr %aa575 ret void576}577 578; Function Attrs: nounwind readnone579declare double @llvm.fabs.f64(double) #1580 581define void @test_dnabs(ptr %aa) #0 {582; SPE-LABEL: test_dnabs:583; SPE: # %bb.0: # %entry584; SPE-NEXT: evldd 4, 0(3)585; SPE-NEXT: efdnabs 4, 4586; SPE-NEXT: evstdd 4, 0(3)587; SPE-NEXT: blr588;589; EFPU2-LABEL: test_dnabs:590; EFPU2: # %bb.0: # %entry591; EFPU2-NEXT: lwz 4, 0(3)592; EFPU2-NEXT: oris 4, 4, 32768593; EFPU2-NEXT: stw 4, 0(3)594; EFPU2-NEXT: blr595 entry:596 %0 = load double, ptr %aa597 %1 = tail call double @llvm.fabs.f64(double %0) #2598 %sub = fsub double -0.000000e+00, %1599 store double %sub, ptr %aa600 ret void601}602 603define double @test_ddiv(double %a, double %b) #0 {604; SPE-LABEL: test_ddiv:605; SPE: # %bb.0: # %entry606; SPE-NEXT: evmergelo 5, 5, 6607; SPE-NEXT: evmergelo 3, 3, 4608; SPE-NEXT: efddiv 4, 3, 5609; SPE-NEXT: evmergehi 3, 4, 4610; SPE-NEXT: blr611;612; EFPU2-LABEL: test_ddiv:613; EFPU2: # %bb.0: # %entry614; EFPU2-NEXT: mflr 0615; EFPU2-NEXT: stwu 1, -16(1)616; EFPU2-NEXT: stw 0, 20(1)617; EFPU2-NEXT: bl __divdf3618; EFPU2-NEXT: lwz 0, 20(1)619; EFPU2-NEXT: addi 1, 1, 16620; EFPU2-NEXT: mtlr 0621; EFPU2-NEXT: blr622entry:623 %v = fdiv double %a, %b624 ret double %v625 626}627 628define double @test_dmul(double %a, double %b) #0 {629; SPE-LABEL: test_dmul:630; SPE: # %bb.0: # %entry631; SPE-NEXT: evmergelo 5, 5, 6632; SPE-NEXT: evmergelo 3, 3, 4633; SPE-NEXT: efdmul 4, 3, 5634; SPE-NEXT: evmergehi 3, 4, 4635; SPE-NEXT: blr636;637; EFPU2-LABEL: test_dmul:638; EFPU2: # %bb.0: # %entry639; EFPU2-NEXT: mflr 0640; EFPU2-NEXT: stwu 1, -16(1)641; EFPU2-NEXT: stw 0, 20(1)642; EFPU2-NEXT: bl __muldf3643; EFPU2-NEXT: lwz 0, 20(1)644; EFPU2-NEXT: addi 1, 1, 16645; EFPU2-NEXT: mtlr 0646; EFPU2-NEXT: blr647 entry:648 %v = fmul double %a, %b649 ret double %v650}651 652define double @test_dadd(double %a, double %b) #0 {653; SPE-LABEL: test_dadd:654; SPE: # %bb.0: # %entry655; SPE-NEXT: evmergelo 5, 5, 6656; SPE-NEXT: evmergelo 3, 3, 4657; SPE-NEXT: efdadd 4, 3, 5658; SPE-NEXT: evmergehi 3, 4, 4659; SPE-NEXT: blr660;661; EFPU2-LABEL: test_dadd:662; EFPU2: # %bb.0: # %entry663; EFPU2-NEXT: mflr 0664; EFPU2-NEXT: stwu 1, -16(1)665; EFPU2-NEXT: stw 0, 20(1)666; EFPU2-NEXT: bl __adddf3667; EFPU2-NEXT: lwz 0, 20(1)668; EFPU2-NEXT: addi 1, 1, 16669; EFPU2-NEXT: mtlr 0670; EFPU2-NEXT: blr671 entry:672 %v = fadd double %a, %b673 ret double %v674}675 676define double @test_dsub(double %a, double %b) #0 {677; SPE-LABEL: test_dsub:678; SPE: # %bb.0: # %entry679; SPE-NEXT: evmergelo 5, 5, 6680; SPE-NEXT: evmergelo 3, 3, 4681; SPE-NEXT: efdsub 4, 3, 5682; SPE-NEXT: evmergehi 3, 4, 4683; SPE-NEXT: blr684;685; EFPU2-LABEL: test_dsub:686; EFPU2: # %bb.0: # %entry687; EFPU2-NEXT: mflr 0688; EFPU2-NEXT: stwu 1, -16(1)689; EFPU2-NEXT: stw 0, 20(1)690; EFPU2-NEXT: bl __subdf3691; EFPU2-NEXT: lwz 0, 20(1)692; EFPU2-NEXT: addi 1, 1, 16693; EFPU2-NEXT: mtlr 0694; EFPU2-NEXT: blr695 entry:696 %v = fsub double %a, %b697 ret double %v698}699 700define double @test_dneg(double %a) #0 {701; SPE-LABEL: test_dneg:702; SPE: # %bb.0: # %entry703; SPE-NEXT: evmergelo 3, 3, 4704; SPE-NEXT: efdneg 4, 3705; SPE-NEXT: evmergehi 3, 4, 4706; SPE-NEXT: blr707;708; EFPU2-LABEL: test_dneg:709; EFPU2: # %bb.0: # %entry710; EFPU2-NEXT: xoris 3, 3, 32768711; EFPU2-NEXT: blr712 entry:713 %v = fsub double -0.0, %a714 ret double %v715}716 717define double @test_stod(float %a) #0 {718; SPE-LABEL: test_stod:719; SPE: # %bb.0: # %entry720; SPE-NEXT: efdcfs 4, 3721; SPE-NEXT: evmergehi 3, 4, 4722; SPE-NEXT: blr723;724; EFPU2-LABEL: test_stod:725; EFPU2: # %bb.0: # %entry726; EFPU2-NEXT: mflr 0727; EFPU2-NEXT: stwu 1, -16(1)728; EFPU2-NEXT: stw 0, 20(1)729; EFPU2-NEXT: bl __extendsfdf2730; EFPU2-NEXT: lwz 0, 20(1)731; EFPU2-NEXT: addi 1, 1, 16732; EFPU2-NEXT: mtlr 0733; EFPU2-NEXT: blr734 entry:735 %v = fpext float %a to double736 ret double %v737}738 739; (un)ordered tests are expanded to une and oeq so verify740define i1 @test_dcmpuno(double %a, double %b) #0 {741; SPE-LABEL: test_dcmpuno:742; SPE: # %bb.0: # %entry743; SPE-NEXT: evmergelo 5, 5, 6744; SPE-NEXT: evmergelo 3, 3, 4745; SPE-NEXT: efdcmpeq 0, 3, 3746; SPE-NEXT: li 3, 0747; SPE-NEXT: bc 4, 1, .LBB35_2748; SPE-NEXT: # %bb.1: # %entry749; SPE-NEXT: efdcmpeq 0, 5, 5750; SPE-NEXT: bclr 12, 1, 0751; SPE-NEXT: .LBB35_2: # %entry752; SPE-NEXT: li 3, 1753; SPE-NEXT: blr754;755; EFPU2-LABEL: test_dcmpuno:756; EFPU2: # %bb.0: # %entry757; EFPU2-NEXT: mflr 0758; EFPU2-NEXT: stwu 1, -16(1)759; EFPU2-NEXT: stw 0, 20(1)760; EFPU2-NEXT: bl __unorddf2761; EFPU2-NEXT: cntlzw 3, 3762; EFPU2-NEXT: not 3, 3763; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31764; EFPU2-NEXT: lwz 0, 20(1)765; EFPU2-NEXT: addi 1, 1, 16766; EFPU2-NEXT: mtlr 0767; EFPU2-NEXT: blr768 entry:769 %r = fcmp uno double %a, %b770 ret i1 %r771}772 773define i1 @test_dcmpord(double %a, double %b) #0 {774; SPE-LABEL: test_dcmpord:775; SPE: # %bb.0: # %entry776; SPE-NEXT: evmergelo 4, 3, 4777; SPE-NEXT: evmergelo 3, 5, 6778; SPE-NEXT: efdcmpeq 0, 3, 3779; SPE-NEXT: li 3, 0780; SPE-NEXT: bclr 4, 1, 0781; SPE-NEXT: # %bb.1: # %entry782; SPE-NEXT: efdcmpeq 0, 4, 4783; SPE-NEXT: bclr 4, 1, 0784; SPE-NEXT: # %bb.2: # %entry785; SPE-NEXT: li 3, 1786; SPE-NEXT: blr787;788; EFPU2-LABEL: test_dcmpord:789; EFPU2: # %bb.0: # %entry790; EFPU2-NEXT: mflr 0791; EFPU2-NEXT: stwu 1, -16(1)792; EFPU2-NEXT: stw 0, 20(1)793; EFPU2-NEXT: bl __unorddf2794; EFPU2-NEXT: cntlzw 3, 3795; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31796; EFPU2-NEXT: lwz 0, 20(1)797; EFPU2-NEXT: addi 1, 1, 16798; EFPU2-NEXT: mtlr 0799; EFPU2-NEXT: blr800 entry:801 %r = fcmp ord double %a, %b802 ret i1 %r803}804 805define i32 @test_dcmpgt(double %a, double %b) #0 {806; SPE-LABEL: test_dcmpgt:807; SPE: # %bb.0: # %entry808; SPE-NEXT: stwu 1, -16(1)809; SPE-NEXT: evmergelo 5, 5, 6810; SPE-NEXT: evmergelo 3, 3, 4811; SPE-NEXT: efdcmpgt 0, 3, 5812; SPE-NEXT: ble 0, .LBB37_2813; SPE-NEXT: # %bb.1: # %tr814; SPE-NEXT: li 3, 1815; SPE-NEXT: b .LBB37_3816; SPE-NEXT: .LBB37_2: # %fa817; SPE-NEXT: li 3, 0818; SPE-NEXT: .LBB37_3: # %ret819; SPE-NEXT: stw 3, 12(1)820; SPE-NEXT: lwz 3, 12(1)821; SPE-NEXT: addi 1, 1, 16822; SPE-NEXT: blr823;824; EFPU2-LABEL: test_dcmpgt:825; EFPU2: # %bb.0: # %entry826; EFPU2-NEXT: mflr 0827; EFPU2-NEXT: stwu 1, -16(1)828; EFPU2-NEXT: stw 0, 20(1)829; EFPU2-NEXT: bl __gtdf2830; EFPU2-NEXT: cmpwi 3, 0831; EFPU2-NEXT: ble 0, .LBB37_2832; EFPU2-NEXT: # %bb.1: # %tr833; EFPU2-NEXT: li 3, 1834; EFPU2-NEXT: b .LBB37_3835; EFPU2-NEXT: .LBB37_2: # %fa836; EFPU2-NEXT: li 3, 0837; EFPU2-NEXT: .LBB37_3: # %ret838; EFPU2-NEXT: stw 3, 12(1)839; EFPU2-NEXT: lwz 3, 12(1)840; EFPU2-NEXT: lwz 0, 20(1)841; EFPU2-NEXT: addi 1, 1, 16842; EFPU2-NEXT: mtlr 0843; EFPU2-NEXT: blr844 entry:845 %r = alloca i32, align 4846 %c = fcmp ogt double %a, %b847 br i1 %c, label %tr, label %fa848tr:849 store i32 1, ptr %r, align 4850 br label %ret851fa:852 store i32 0, ptr %r, align 4853 br label %ret854ret:855 %0 = load i32, ptr %r, align 4856 ret i32 %0857}858 859define i32 @test_dcmpugt(double %a, double %b) #0 {860; SPE-LABEL: test_dcmpugt:861; SPE: # %bb.0: # %entry862; SPE-NEXT: stwu 1, -16(1)863; SPE-NEXT: evmergelo 3, 3, 4864; SPE-NEXT: evmergelo 4, 5, 6865; SPE-NEXT: efdcmpeq 0, 4, 4866; SPE-NEXT: bc 4, 1, .LBB38_4867; SPE-NEXT: # %bb.1: # %entry868; SPE-NEXT: efdcmpeq 0, 3, 3869; SPE-NEXT: bc 4, 1, .LBB38_4870; SPE-NEXT: # %bb.2: # %entry871; SPE-NEXT: efdcmpgt 0, 3, 4872; SPE-NEXT: bc 12, 1, .LBB38_4873; SPE-NEXT: # %bb.3: # %fa874; SPE-NEXT: li 3, 0875; SPE-NEXT: b .LBB38_5876; SPE-NEXT: .LBB38_4: # %tr877; SPE-NEXT: li 3, 1878; SPE-NEXT: .LBB38_5: # %ret879; SPE-NEXT: stw 3, 12(1)880; SPE-NEXT: lwz 3, 12(1)881; SPE-NEXT: addi 1, 1, 16882; SPE-NEXT: blr883;884; EFPU2-LABEL: test_dcmpugt:885; EFPU2: # %bb.0: # %entry886; EFPU2-NEXT: mflr 0887; EFPU2-NEXT: stwu 1, -16(1)888; EFPU2-NEXT: stw 0, 20(1)889; EFPU2-NEXT: bl __ledf2890; EFPU2-NEXT: cmpwi 3, 0891; EFPU2-NEXT: ble 0, .LBB38_2892; EFPU2-NEXT: # %bb.1: # %tr893; EFPU2-NEXT: li 3, 1894; EFPU2-NEXT: b .LBB38_3895; EFPU2-NEXT: .LBB38_2: # %fa896; EFPU2-NEXT: li 3, 0897; EFPU2-NEXT: .LBB38_3: # %ret898; EFPU2-NEXT: stw 3, 12(1)899; EFPU2-NEXT: lwz 3, 12(1)900; EFPU2-NEXT: lwz 0, 20(1)901; EFPU2-NEXT: addi 1, 1, 16902; EFPU2-NEXT: mtlr 0903; EFPU2-NEXT: blr904 entry:905 %r = alloca i32, align 4906 %c = fcmp ugt double %a, %b907 br i1 %c, label %tr, label %fa908tr:909 store i32 1, ptr %r, align 4910 br label %ret911fa:912 store i32 0, ptr %r, align 4913 br label %ret914ret:915 %0 = load i32, ptr %r, align 4916 ret i32 %0917}918 919define i32 @test_dcmple(double %a, double %b) #0 {920; SPE-LABEL: test_dcmple:921; SPE: # %bb.0: # %entry922; SPE-NEXT: stwu 1, -16(1)923; SPE-NEXT: evmergelo 5, 5, 6924; SPE-NEXT: evmergelo 3, 3, 4925; SPE-NEXT: efdcmpgt 0, 3, 5926; SPE-NEXT: bgt 0, .LBB39_2927; SPE-NEXT: # %bb.1: # %tr928; SPE-NEXT: li 3, 1929; SPE-NEXT: b .LBB39_3930; SPE-NEXT: .LBB39_2: # %fa931; SPE-NEXT: li 3, 0932; SPE-NEXT: .LBB39_3: # %ret933; SPE-NEXT: stw 3, 12(1)934; SPE-NEXT: lwz 3, 12(1)935; SPE-NEXT: addi 1, 1, 16936; SPE-NEXT: blr937;938; EFPU2-LABEL: test_dcmple:939; EFPU2: # %bb.0: # %entry940; EFPU2-NEXT: mflr 0941; EFPU2-NEXT: stwu 1, -16(1)942; EFPU2-NEXT: stw 0, 20(1)943; EFPU2-NEXT: bl __gtdf2944; EFPU2-NEXT: cmpwi 3, 0945; EFPU2-NEXT: bgt 0, .LBB39_2946; EFPU2-NEXT: # %bb.1: # %tr947; EFPU2-NEXT: li 3, 1948; EFPU2-NEXT: b .LBB39_3949; EFPU2-NEXT: .LBB39_2: # %fa950; EFPU2-NEXT: li 3, 0951; EFPU2-NEXT: .LBB39_3: # %ret952; EFPU2-NEXT: stw 3, 12(1)953; EFPU2-NEXT: lwz 3, 12(1)954; EFPU2-NEXT: lwz 0, 20(1)955; EFPU2-NEXT: addi 1, 1, 16956; EFPU2-NEXT: mtlr 0957; EFPU2-NEXT: blr958 entry:959 %r = alloca i32, align 4960 %c = fcmp ule double %a, %b961 br i1 %c, label %tr, label %fa962tr:963 store i32 1, ptr %r, align 4964 br label %ret965fa:966 store i32 0, ptr %r, align 4967 br label %ret968ret:969 %0 = load i32, ptr %r, align 4970 ret i32 %0971}972 973define i32 @test_dcmpule(double %a, double %b) #0 {974; SPE-LABEL: test_dcmpule:975; SPE: # %bb.0: # %entry976; SPE-NEXT: stwu 1, -16(1)977; SPE-NEXT: evmergelo 5, 5, 6978; SPE-NEXT: evmergelo 3, 3, 4979; SPE-NEXT: efdcmpgt 0, 3, 5980; SPE-NEXT: bgt 0, .LBB40_2981; SPE-NEXT: # %bb.1: # %tr982; SPE-NEXT: li 3, 1983; SPE-NEXT: b .LBB40_3984; SPE-NEXT: .LBB40_2: # %fa985; SPE-NEXT: li 3, 0986; SPE-NEXT: .LBB40_3: # %ret987; SPE-NEXT: stw 3, 12(1)988; SPE-NEXT: lwz 3, 12(1)989; SPE-NEXT: addi 1, 1, 16990; SPE-NEXT: blr991;992; EFPU2-LABEL: test_dcmpule:993; EFPU2: # %bb.0: # %entry994; EFPU2-NEXT: mflr 0995; EFPU2-NEXT: stwu 1, -16(1)996; EFPU2-NEXT: stw 0, 20(1)997; EFPU2-NEXT: bl __gtdf2998; EFPU2-NEXT: cmpwi 3, 0999; EFPU2-NEXT: bgt 0, .LBB40_21000; EFPU2-NEXT: # %bb.1: # %tr1001; EFPU2-NEXT: li 3, 11002; EFPU2-NEXT: b .LBB40_31003; EFPU2-NEXT: .LBB40_2: # %fa1004; EFPU2-NEXT: li 3, 01005; EFPU2-NEXT: .LBB40_3: # %ret1006; EFPU2-NEXT: stw 3, 12(1)1007; EFPU2-NEXT: lwz 3, 12(1)1008; EFPU2-NEXT: lwz 0, 20(1)1009; EFPU2-NEXT: addi 1, 1, 161010; EFPU2-NEXT: mtlr 01011; EFPU2-NEXT: blr1012 entry:1013 %r = alloca i32, align 41014 %c = fcmp ule double %a, %b1015 br i1 %c, label %tr, label %fa1016tr:1017 store i32 1, ptr %r, align 41018 br label %ret1019fa:1020 store i32 0, ptr %r, align 41021 br label %ret1022ret:1023 %0 = load i32, ptr %r, align 41024 ret i32 %01025}1026 1027; The type of comparison found in C's if (x == y)1028define i32 @test_dcmpeq(double %a, double %b) #0 {1029; SPE-LABEL: test_dcmpeq:1030; SPE: # %bb.0: # %entry1031; SPE-NEXT: stwu 1, -16(1)1032; SPE-NEXT: evmergelo 5, 5, 61033; SPE-NEXT: evmergelo 3, 3, 41034; SPE-NEXT: efdcmpeq 0, 3, 51035; SPE-NEXT: ble 0, .LBB41_21036; SPE-NEXT: # %bb.1: # %tr1037; SPE-NEXT: li 3, 11038; SPE-NEXT: b .LBB41_31039; SPE-NEXT: .LBB41_2: # %fa1040; SPE-NEXT: li 3, 01041; SPE-NEXT: .LBB41_3: # %ret1042; SPE-NEXT: stw 3, 12(1)1043; SPE-NEXT: lwz 3, 12(1)1044; SPE-NEXT: addi 1, 1, 161045; SPE-NEXT: blr1046;1047; EFPU2-LABEL: test_dcmpeq:1048; EFPU2: # %bb.0: # %entry1049; EFPU2-NEXT: mflr 01050; EFPU2-NEXT: stwu 1, -16(1)1051; EFPU2-NEXT: stw 0, 20(1)1052; EFPU2-NEXT: bl __nedf21053; EFPU2-NEXT: cmplwi 3, 01054; EFPU2-NEXT: bne 0, .LBB41_21055; EFPU2-NEXT: # %bb.1: # %tr1056; EFPU2-NEXT: li 3, 11057; EFPU2-NEXT: b .LBB41_31058; EFPU2-NEXT: .LBB41_2: # %fa1059; EFPU2-NEXT: li 3, 01060; EFPU2-NEXT: .LBB41_3: # %ret1061; EFPU2-NEXT: stw 3, 12(1)1062; EFPU2-NEXT: lwz 3, 12(1)1063; EFPU2-NEXT: lwz 0, 20(1)1064; EFPU2-NEXT: addi 1, 1, 161065; EFPU2-NEXT: mtlr 01066; EFPU2-NEXT: blr1067 entry:1068 %r = alloca i32, align 41069 %c = fcmp oeq double %a, %b1070 br i1 %c, label %tr, label %fa1071tr:1072 store i32 1, ptr %r, align 41073 br label %ret1074fa:1075 store i32 0, ptr %r, align 41076 br label %ret1077ret:1078 %0 = load i32, ptr %r, align 41079 ret i32 %01080}1081 1082define i32 @test_dcmpueq(double %a, double %b) #0 {1083; SPE-LABEL: test_dcmpueq:1084; SPE: # %bb.0: # %entry1085; SPE-NEXT: stwu 1, -16(1)1086; SPE-NEXT: evmergelo 5, 5, 61087; SPE-NEXT: evmergelo 3, 3, 41088; SPE-NEXT: efdcmplt 0, 3, 51089; SPE-NEXT: bc 12, 1, .LBB42_31090; SPE-NEXT: # %bb.1: # %entry1091; SPE-NEXT: efdcmpgt 0, 3, 51092; SPE-NEXT: bc 12, 1, .LBB42_31093; SPE-NEXT: # %bb.2: # %tr1094; SPE-NEXT: li 3, 11095; SPE-NEXT: b .LBB42_41096; SPE-NEXT: .LBB42_3: # %fa1097; SPE-NEXT: li 3, 01098; SPE-NEXT: .LBB42_4: # %ret1099; SPE-NEXT: stw 3, 12(1)1100; SPE-NEXT: lwz 3, 12(1)1101; SPE-NEXT: addi 1, 1, 161102; SPE-NEXT: blr1103;1104; EFPU2-LABEL: test_dcmpueq:1105; EFPU2: # %bb.0: # %entry1106; EFPU2-NEXT: mflr 01107; EFPU2-NEXT: stwu 1, -48(1)1108; EFPU2-NEXT: mfcr 121109; EFPU2-NEXT: stw 0, 52(1)1110; EFPU2-NEXT: stw 12, 24(1)1111; EFPU2-NEXT: stw 27, 28(1) # 4-byte Folded Spill1112; EFPU2-NEXT: mr 27, 31113; EFPU2-NEXT: stw 28, 32(1) # 4-byte Folded Spill1114; EFPU2-NEXT: mr 28, 41115; EFPU2-NEXT: stw 29, 36(1) # 4-byte Folded Spill1116; EFPU2-NEXT: mr 29, 51117; EFPU2-NEXT: stw 30, 40(1) # 4-byte Folded Spill1118; EFPU2-NEXT: mr 30, 61119; EFPU2-NEXT: bl __eqdf21120; EFPU2-NEXT: cmpwi 2, 3, 01121; EFPU2-NEXT: mr 3, 271122; EFPU2-NEXT: mr 4, 281123; EFPU2-NEXT: mr 5, 291124; EFPU2-NEXT: mr 6, 301125; EFPU2-NEXT: bl __unorddf21126; EFPU2-NEXT: bc 12, 10, .LBB42_31127; EFPU2-NEXT: # %bb.1: # %entry1128; EFPU2-NEXT: cmpwi 3, 01129; EFPU2-NEXT: bc 4, 2, .LBB42_31130; EFPU2-NEXT: # %bb.2: # %fa1131; EFPU2-NEXT: li 3, 01132; EFPU2-NEXT: b .LBB42_41133; EFPU2-NEXT: .LBB42_3: # %tr1134; EFPU2-NEXT: li 3, 11135; EFPU2-NEXT: .LBB42_4: # %ret1136; EFPU2-NEXT: stw 3, 20(1)1137; EFPU2-NEXT: lwz 3, 20(1)1138; EFPU2-NEXT: lwz 30, 40(1) # 4-byte Folded Reload1139; EFPU2-NEXT: lwz 29, 36(1) # 4-byte Folded Reload1140; EFPU2-NEXT: lwz 28, 32(1) # 4-byte Folded Reload1141; EFPU2-NEXT: lwz 12, 24(1)1142; EFPU2-NEXT: lwz 27, 28(1) # 4-byte Folded Reload1143; EFPU2-NEXT: mtcrf 32, 12 # cr21144; EFPU2-NEXT: lwz 0, 52(1)1145; EFPU2-NEXT: addi 1, 1, 481146; EFPU2-NEXT: mtlr 01147; EFPU2-NEXT: blr1148 entry:1149 %r = alloca i32, align 41150 %c = fcmp ueq double %a, %b1151 br i1 %c, label %tr, label %fa1152tr:1153 store i32 1, ptr %r, align 41154 br label %ret1155fa:1156 store i32 0, ptr %r, align 41157 br label %ret1158ret:1159 %0 = load i32, ptr %r, align 41160 ret i32 %01161}1162 1163define i1 @test_dcmpne(double %a, double %b) #0 {1164; SPE-LABEL: test_dcmpne:1165; SPE: # %bb.0: # %entry1166; SPE-NEXT: evmergelo 5, 5, 61167; SPE-NEXT: evmergelo 4, 3, 41168; SPE-NEXT: li 3, 01169; SPE-NEXT: efdcmplt 0, 4, 51170; SPE-NEXT: bc 12, 1, .LBB43_21171; SPE-NEXT: # %bb.1: # %entry1172; SPE-NEXT: efdcmpgt 0, 4, 51173; SPE-NEXT: bclr 4, 1, 01174; SPE-NEXT: .LBB43_2: # %entry1175; SPE-NEXT: li 3, 11176; SPE-NEXT: blr1177;1178; EFPU2-LABEL: test_dcmpne:1179; EFPU2: # %bb.0: # %entry1180; EFPU2-NEXT: mflr 01181; EFPU2-NEXT: stwu 1, -48(1)1182; EFPU2-NEXT: mfcr 121183; EFPU2-NEXT: stw 0, 52(1)1184; EFPU2-NEXT: stw 12, 24(1)1185; EFPU2-NEXT: stw 27, 28(1) # 4-byte Folded Spill1186; EFPU2-NEXT: mr 27, 31187; EFPU2-NEXT: stw 28, 32(1) # 4-byte Folded Spill1188; EFPU2-NEXT: mr 28, 41189; EFPU2-NEXT: stw 29, 36(1) # 4-byte Folded Spill1190; EFPU2-NEXT: mr 29, 51191; EFPU2-NEXT: stw 30, 40(1) # 4-byte Folded Spill1192; EFPU2-NEXT: mr 30, 61193; EFPU2-NEXT: bl __unorddf21194; EFPU2-NEXT: cmpwi 2, 3, 01195; EFPU2-NEXT: mr 3, 271196; EFPU2-NEXT: mr 4, 281197; EFPU2-NEXT: mr 5, 291198; EFPU2-NEXT: mr 6, 301199; EFPU2-NEXT: bl __eqdf21200; EFPU2-NEXT: mr 4, 31201; EFPU2-NEXT: li 3, 01202; EFPU2-NEXT: bc 4, 10, .LBB43_31203; EFPU2-NEXT: # %bb.1: # %entry1204; EFPU2-NEXT: cmpwi 4, 01205; EFPU2-NEXT: bc 12, 2, .LBB43_31206; EFPU2-NEXT: # %bb.2: # %entry1207; EFPU2-NEXT: li 3, 11208; EFPU2-NEXT: .LBB43_3: # %entry1209; EFPU2-NEXT: lwz 30, 40(1) # 4-byte Folded Reload1210; EFPU2-NEXT: lwz 29, 36(1) # 4-byte Folded Reload1211; EFPU2-NEXT: lwz 28, 32(1) # 4-byte Folded Reload1212; EFPU2-NEXT: lwz 12, 24(1)1213; EFPU2-NEXT: lwz 27, 28(1) # 4-byte Folded Reload1214; EFPU2-NEXT: mtcrf 32, 12 # cr21215; EFPU2-NEXT: lwz 0, 52(1)1216; EFPU2-NEXT: addi 1, 1, 481217; EFPU2-NEXT: mtlr 01218; EFPU2-NEXT: blr1219 entry:1220 %r = fcmp one double %a, %b1221 ret i1 %r1222}1223 1224define i32 @test_dcmpune(double %a, double %b) #0 {1225; SPE-LABEL: test_dcmpune:1226; SPE: # %bb.0: # %entry1227; SPE-NEXT: stwu 1, -16(1)1228; SPE-NEXT: evmergelo 5, 5, 61229; SPE-NEXT: evmergelo 3, 3, 41230; SPE-NEXT: efdcmpeq 0, 3, 51231; SPE-NEXT: bgt 0, .LBB44_21232; SPE-NEXT: # %bb.1: # %tr1233; SPE-NEXT: li 3, 11234; SPE-NEXT: b .LBB44_31235; SPE-NEXT: .LBB44_2: # %fa1236; SPE-NEXT: li 3, 01237; SPE-NEXT: .LBB44_3: # %ret1238; SPE-NEXT: stw 3, 12(1)1239; SPE-NEXT: lwz 3, 12(1)1240; SPE-NEXT: addi 1, 1, 161241; SPE-NEXT: blr1242;1243; EFPU2-LABEL: test_dcmpune:1244; EFPU2: # %bb.0: # %entry1245; EFPU2-NEXT: mflr 01246; EFPU2-NEXT: stwu 1, -16(1)1247; EFPU2-NEXT: stw 0, 20(1)1248; EFPU2-NEXT: bl __eqdf21249; EFPU2-NEXT: cmplwi 3, 01250; EFPU2-NEXT: beq 0, .LBB44_21251; EFPU2-NEXT: # %bb.1: # %tr1252; EFPU2-NEXT: li 3, 11253; EFPU2-NEXT: b .LBB44_31254; EFPU2-NEXT: .LBB44_2: # %fa1255; EFPU2-NEXT: li 3, 01256; EFPU2-NEXT: .LBB44_3: # %ret1257; EFPU2-NEXT: stw 3, 12(1)1258; EFPU2-NEXT: lwz 3, 12(1)1259; EFPU2-NEXT: lwz 0, 20(1)1260; EFPU2-NEXT: addi 1, 1, 161261; EFPU2-NEXT: mtlr 01262; EFPU2-NEXT: blr1263 entry:1264 %r = alloca i32, align 41265 %c = fcmp une double %a, %b1266 br i1 %c, label %tr, label %fa1267tr:1268 store i32 1, ptr %r, align 41269 br label %ret1270fa:1271 store i32 0, ptr %r, align 41272 br label %ret1273ret:1274 %0 = load i32, ptr %r, align 41275 ret i32 %01276}1277 1278define i32 @test_dcmplt(double %a, double %b) #0 {1279; SPE-LABEL: test_dcmplt:1280; SPE: # %bb.0: # %entry1281; SPE-NEXT: stwu 1, -16(1)1282; SPE-NEXT: evmergelo 5, 5, 61283; SPE-NEXT: evmergelo 3, 3, 41284; SPE-NEXT: efdcmplt 0, 3, 51285; SPE-NEXT: ble 0, .LBB45_21286; SPE-NEXT: # %bb.1: # %tr1287; SPE-NEXT: li 3, 11288; SPE-NEXT: b .LBB45_31289; SPE-NEXT: .LBB45_2: # %fa1290; SPE-NEXT: li 3, 01291; SPE-NEXT: .LBB45_3: # %ret1292; SPE-NEXT: stw 3, 12(1)1293; SPE-NEXT: lwz 3, 12(1)1294; SPE-NEXT: addi 1, 1, 161295; SPE-NEXT: blr1296;1297; EFPU2-LABEL: test_dcmplt:1298; EFPU2: # %bb.0: # %entry1299; EFPU2-NEXT: mflr 01300; EFPU2-NEXT: stwu 1, -16(1)1301; EFPU2-NEXT: stw 0, 20(1)1302; EFPU2-NEXT: bl __ltdf21303; EFPU2-NEXT: cmpwi 3, 01304; EFPU2-NEXT: bge 0, .LBB45_21305; EFPU2-NEXT: # %bb.1: # %tr1306; EFPU2-NEXT: li 3, 11307; EFPU2-NEXT: b .LBB45_31308; EFPU2-NEXT: .LBB45_2: # %fa1309; EFPU2-NEXT: li 3, 01310; EFPU2-NEXT: .LBB45_3: # %ret1311; EFPU2-NEXT: stw 3, 12(1)1312; EFPU2-NEXT: lwz 3, 12(1)1313; EFPU2-NEXT: lwz 0, 20(1)1314; EFPU2-NEXT: addi 1, 1, 161315; EFPU2-NEXT: mtlr 01316; EFPU2-NEXT: blr1317 entry:1318 %r = alloca i32, align 41319 %c = fcmp olt double %a, %b1320 br i1 %c, label %tr, label %fa1321tr:1322 store i32 1, ptr %r, align 41323 br label %ret1324fa:1325 store i32 0, ptr %r, align 41326 br label %ret1327ret:1328 %0 = load i32, ptr %r, align 41329 ret i32 %01330}1331 1332define i32 @test_dcmpult(double %a, double %b) #0 {1333; SPE-LABEL: test_dcmpult:1334; SPE: # %bb.0: # %entry1335; SPE-NEXT: stwu 1, -16(1)1336; SPE-NEXT: evmergelo 3, 3, 41337; SPE-NEXT: evmergelo 4, 5, 61338; SPE-NEXT: efdcmpeq 0, 4, 41339; SPE-NEXT: bc 4, 1, .LBB46_41340; SPE-NEXT: # %bb.1: # %entry1341; SPE-NEXT: efdcmpeq 0, 3, 31342; SPE-NEXT: bc 4, 1, .LBB46_41343; SPE-NEXT: # %bb.2: # %entry1344; SPE-NEXT: efdcmplt 0, 3, 41345; SPE-NEXT: bc 12, 1, .LBB46_41346; SPE-NEXT: # %bb.3: # %fa1347; SPE-NEXT: li 3, 01348; SPE-NEXT: b .LBB46_51349; SPE-NEXT: .LBB46_4: # %tr1350; SPE-NEXT: li 3, 11351; SPE-NEXT: .LBB46_5: # %ret1352; SPE-NEXT: stw 3, 12(1)1353; SPE-NEXT: lwz 3, 12(1)1354; SPE-NEXT: addi 1, 1, 161355; SPE-NEXT: blr1356;1357; EFPU2-LABEL: test_dcmpult:1358; EFPU2: # %bb.0: # %entry1359; EFPU2-NEXT: mflr 01360; EFPU2-NEXT: stwu 1, -16(1)1361; EFPU2-NEXT: stw 0, 20(1)1362; EFPU2-NEXT: bl __gedf21363; EFPU2-NEXT: cmpwi 3, 01364; EFPU2-NEXT: bge 0, .LBB46_21365; EFPU2-NEXT: # %bb.1: # %tr1366; EFPU2-NEXT: li 3, 11367; EFPU2-NEXT: b .LBB46_31368; EFPU2-NEXT: .LBB46_2: # %fa1369; EFPU2-NEXT: li 3, 01370; EFPU2-NEXT: .LBB46_3: # %ret1371; EFPU2-NEXT: stw 3, 12(1)1372; EFPU2-NEXT: lwz 3, 12(1)1373; EFPU2-NEXT: lwz 0, 20(1)1374; EFPU2-NEXT: addi 1, 1, 161375; EFPU2-NEXT: mtlr 01376; EFPU2-NEXT: blr1377 entry:1378 %r = alloca i32, align 41379 %c = fcmp ult double %a, %b1380 br i1 %c, label %tr, label %fa1381tr:1382 store i32 1, ptr %r, align 41383 br label %ret1384fa:1385 store i32 0, ptr %r, align 41386 br label %ret1387ret:1388 %0 = load i32, ptr %r, align 41389 ret i32 %01390}1391 1392define i1 @test_dcmpge(double %a, double %b) #0 {1393; SPE-LABEL: test_dcmpge:1394; SPE: # %bb.0: # %entry1395; SPE-NEXT: evmergelo 4, 3, 41396; SPE-NEXT: evmergelo 5, 5, 61397; SPE-NEXT: li 3, 01398; SPE-NEXT: efdcmpeq 0, 5, 51399; SPE-NEXT: bclr 4, 1, 01400; SPE-NEXT: # %bb.1: # %entry1401; SPE-NEXT: efdcmpeq 0, 4, 41402; SPE-NEXT: bclr 4, 1, 01403; SPE-NEXT: # %bb.2: # %entry1404; SPE-NEXT: efdcmplt 0, 4, 51405; SPE-NEXT: bclr 12, 1, 01406; SPE-NEXT: # %bb.3: # %entry1407; SPE-NEXT: li 3, 11408; SPE-NEXT: blr1409;1410; EFPU2-LABEL: test_dcmpge:1411; EFPU2: # %bb.0: # %entry1412; EFPU2-NEXT: mflr 01413; EFPU2-NEXT: stwu 1, -16(1)1414; EFPU2-NEXT: stw 0, 20(1)1415; EFPU2-NEXT: bl __gedf21416; EFPU2-NEXT: not 3, 31417; EFPU2-NEXT: srwi 3, 3, 311418; EFPU2-NEXT: lwz 0, 20(1)1419; EFPU2-NEXT: addi 1, 1, 161420; EFPU2-NEXT: mtlr 01421; EFPU2-NEXT: blr1422 entry:1423 %r = fcmp oge double %a, %b1424 ret i1 %r1425}1426 1427define i32 @test_dcmpuge(double %a, double %b) #0 {1428; SPE-LABEL: test_dcmpuge:1429; SPE: # %bb.0: # %entry1430; SPE-NEXT: stwu 1, -16(1)1431; SPE-NEXT: evmergelo 5, 5, 61432; SPE-NEXT: evmergelo 3, 3, 41433; SPE-NEXT: efdcmplt 0, 3, 51434; SPE-NEXT: bgt 0, .LBB48_21435; SPE-NEXT: # %bb.1: # %tr1436; SPE-NEXT: li 3, 11437; SPE-NEXT: b .LBB48_31438; SPE-NEXT: .LBB48_2: # %fa1439; SPE-NEXT: li 3, 01440; SPE-NEXT: .LBB48_3: # %ret1441; SPE-NEXT: stw 3, 12(1)1442; SPE-NEXT: lwz 3, 12(1)1443; SPE-NEXT: addi 1, 1, 161444; SPE-NEXT: blr1445;1446; EFPU2-LABEL: test_dcmpuge:1447; EFPU2: # %bb.0: # %entry1448; EFPU2-NEXT: mflr 01449; EFPU2-NEXT: stwu 1, -16(1)1450; EFPU2-NEXT: stw 0, 20(1)1451; EFPU2-NEXT: bl __ltdf21452; EFPU2-NEXT: cmpwi 3, 01453; EFPU2-NEXT: blt 0, .LBB48_21454; EFPU2-NEXT: # %bb.1: # %tr1455; EFPU2-NEXT: li 3, 11456; EFPU2-NEXT: b .LBB48_31457; EFPU2-NEXT: .LBB48_2: # %fa1458; EFPU2-NEXT: li 3, 01459; EFPU2-NEXT: .LBB48_3: # %ret1460; EFPU2-NEXT: stw 3, 12(1)1461; EFPU2-NEXT: lwz 3, 12(1)1462; EFPU2-NEXT: lwz 0, 20(1)1463; EFPU2-NEXT: addi 1, 1, 161464; EFPU2-NEXT: mtlr 01465; EFPU2-NEXT: blr1466 entry:1467 %r = alloca i32, align 41468 %c = fcmp uge double %a, %b1469 br i1 %c, label %tr, label %fa1470tr:1471 store i32 1, ptr %r, align 41472 br label %ret1473fa:1474 store i32 0, ptr %r, align 41475 br label %ret1476ret:1477 %0 = load i32, ptr %r, align 41478 ret i32 %01479}1480 1481define double @test_dselect(double %a, double %b, i1 %c) #0 {1482; SPE-LABEL: test_dselect:1483; SPE: # %bb.0: # %entry1484; SPE-NEXT: andi. 7, 7, 11485; SPE-NEXT: evmergelo 5, 5, 61486; SPE-NEXT: evmergelo 4, 3, 41487; SPE-NEXT: bc 12, 1, .LBB49_21488; SPE-NEXT: # %bb.1: # %entry1489; SPE-NEXT: evor 4, 5, 51490; SPE-NEXT: .LBB49_2: # %entry1491; SPE-NEXT: evmergehi 3, 4, 41492; SPE-NEXT: blr1493;1494; EFPU2-LABEL: test_dselect:1495; EFPU2: # %bb.0: # %entry1496; EFPU2-NEXT: andi. 7, 7, 11497; EFPU2-NEXT: bc 12, 1, .LBB49_21498; EFPU2-NEXT: # %bb.1: # %entry1499; EFPU2-NEXT: mr 3, 51500; EFPU2-NEXT: .LBB49_2: # %entry1501; EFPU2-NEXT: bclr 12, 1, 01502; EFPU2-NEXT: # %bb.3: # %entry1503; EFPU2-NEXT: mr 4, 61504; EFPU2-NEXT: blr1505entry:1506 %r = select i1 %c, double %a, double %b1507 ret double %r1508}1509 1510define i32 @test_dtoui(double %a) #0 {1511; SPE-LABEL: test_dtoui:1512; SPE: # %bb.0: # %entry1513; SPE-NEXT: evmergelo 3, 3, 41514; SPE-NEXT: efdctuiz 3, 31515; SPE-NEXT: blr1516;1517; EFPU2-LABEL: test_dtoui:1518; EFPU2: # %bb.0: # %entry1519; EFPU2-NEXT: mflr 01520; EFPU2-NEXT: stwu 1, -16(1)1521; EFPU2-NEXT: stw 0, 20(1)1522; EFPU2-NEXT: bl __fixunsdfsi1523; EFPU2-NEXT: lwz 0, 20(1)1524; EFPU2-NEXT: addi 1, 1, 161525; EFPU2-NEXT: mtlr 01526; EFPU2-NEXT: blr1527entry:1528 %v = fptoui double %a to i321529 ret i32 %v1530}1531 1532define i32 @test_dtosi(double %a) #0 {1533; SPE-LABEL: test_dtosi:1534; SPE: # %bb.0: # %entry1535; SPE-NEXT: evmergelo 3, 3, 41536; SPE-NEXT: efdctsiz 3, 31537; SPE-NEXT: blr1538;1539; EFPU2-LABEL: test_dtosi:1540; EFPU2: # %bb.0: # %entry1541; EFPU2-NEXT: mflr 01542; EFPU2-NEXT: stwu 1, -16(1)1543; EFPU2-NEXT: stw 0, 20(1)1544; EFPU2-NEXT: bl __fixdfsi1545; EFPU2-NEXT: lwz 0, 20(1)1546; EFPU2-NEXT: addi 1, 1, 161547; EFPU2-NEXT: mtlr 01548; EFPU2-NEXT: blr1549entry:1550 %v = fptosi double %a to i321551 ret i32 %v1552}1553 1554define double @test_dfromui(i32 %a) #0 {1555; SPE-LABEL: test_dfromui:1556; SPE: # %bb.0: # %entry1557; SPE-NEXT: efdcfui 4, 31558; SPE-NEXT: evmergehi 3, 4, 41559; SPE-NEXT: blr1560;1561; EFPU2-LABEL: test_dfromui:1562; EFPU2: # %bb.0: # %entry1563; EFPU2-NEXT: mflr 01564; EFPU2-NEXT: stwu 1, -16(1)1565; EFPU2-NEXT: stw 0, 20(1)1566; EFPU2-NEXT: bl __floatunsidf1567; EFPU2-NEXT: lwz 0, 20(1)1568; EFPU2-NEXT: addi 1, 1, 161569; EFPU2-NEXT: mtlr 01570; EFPU2-NEXT: blr1571entry:1572 %v = uitofp i32 %a to double1573 ret double %v1574}1575 1576define double @test_dfromsi(i32 %a) #0 {1577; SPE-LABEL: test_dfromsi:1578; SPE: # %bb.0: # %entry1579; SPE-NEXT: efdcfsi 4, 31580; SPE-NEXT: evmergehi 3, 4, 41581; SPE-NEXT: blr1582;1583; EFPU2-LABEL: test_dfromsi:1584; EFPU2: # %bb.0: # %entry1585; EFPU2-NEXT: mflr 01586; EFPU2-NEXT: stwu 1, -16(1)1587; EFPU2-NEXT: stw 0, 20(1)1588; EFPU2-NEXT: bl __floatsidf1589; EFPU2-NEXT: lwz 0, 20(1)1590; EFPU2-NEXT: addi 1, 1, 161591; EFPU2-NEXT: mtlr 01592; EFPU2-NEXT: blr1593entry:1594 %v = sitofp i32 %a to double1595 ret double %v1596}1597 1598declare double @test_spill_spe_regs(double, double);1599define dso_local void @test_func2() #0 {1600; CHECK-LABEL: test_func2:1601; CHECK: # %bb.0: # %entry1602; CHECK-NEXT: blr1603entry:1604 ret void1605}1606 1607declare void @test_memset(ptr nocapture writeonly, i8, i32, i1)1608@global_var1 = global i32 0, align 41609define double @test_spill(double %a, i32 %a1, i64 %a2, ptr %a3, ptr %a4, ptr %a5) #0 {1610; SPE-LABEL: test_spill:1611; SPE: # %bb.0: # %entry1612; SPE-NEXT: mflr 01613; SPE-NEXT: stwu 1, -288(1)1614; SPE-NEXT: li 5, 2561615; SPE-NEXT: stw 0, 292(1)1616; SPE-NEXT: lis 6, .LCPI55_0@ha1617; SPE-NEXT: evstddx 30, 1, 5 # 8-byte Folded Spill1618; SPE-NEXT: li 5, .LCPI55_0@l1619; SPE-NEXT: evlddx 5, 6, 51620; SPE-NEXT: stw 31, 284(1) # 4-byte Folded Spill1621; SPE-NEXT: evstdd 14, 128(1) # 8-byte Folded Spill1622; SPE-NEXT: evstdd 15, 136(1) # 8-byte Folded Spill1623; SPE-NEXT: evstdd 16, 144(1) # 8-byte Folded Spill1624; SPE-NEXT: evstdd 17, 152(1) # 8-byte Folded Spill1625; SPE-NEXT: evstdd 18, 160(1) # 8-byte Folded Spill1626; SPE-NEXT: evstdd 19, 168(1) # 8-byte Folded Spill1627; SPE-NEXT: evstdd 20, 176(1) # 8-byte Folded Spill1628; SPE-NEXT: evstdd 21, 184(1) # 8-byte Folded Spill1629; SPE-NEXT: evstdd 22, 192(1) # 8-byte Folded Spill1630; SPE-NEXT: evstdd 23, 200(1) # 8-byte Folded Spill1631; SPE-NEXT: evstdd 24, 208(1) # 8-byte Folded Spill1632; SPE-NEXT: evstdd 25, 216(1) # 8-byte Folded Spill1633; SPE-NEXT: evstdd 26, 224(1) # 8-byte Folded Spill1634; SPE-NEXT: evstdd 27, 232(1) # 8-byte Folded Spill1635; SPE-NEXT: evstdd 28, 240(1) # 8-byte Folded Spill1636; SPE-NEXT: evstdd 29, 248(1) # 8-byte Folded Spill1637; SPE-NEXT: evmergelo 3, 3, 41638; SPE-NEXT: lwz 4, 296(1)1639; SPE-NEXT: efdadd 3, 3, 31640; SPE-NEXT: efdadd 3, 3, 51641; SPE-NEXT: evstdd 3, 24(1) # 8-byte Folded Spill1642; SPE-NEXT: stw 4, 20(1) # 4-byte Folded Spill1643; SPE-NEXT: #APP1644; SPE-NEXT: #NO_APP1645; SPE-NEXT: addi 3, 1, 761646; SPE-NEXT: li 4, 01647; SPE-NEXT: li 5, 241648; SPE-NEXT: li 6, 11649; SPE-NEXT: li 30, 01650; SPE-NEXT: bl test_memset1651; SPE-NEXT: lwz 3, 20(1) # 4-byte Folded Reload1652; SPE-NEXT: stw 30, 0(3)1653; SPE-NEXT: bl test_func21654; SPE-NEXT: addi 3, 1, 321655; SPE-NEXT: li 4, 01656; SPE-NEXT: li 5, 201657; SPE-NEXT: li 6, 11658; SPE-NEXT: bl test_memset1659; SPE-NEXT: evldd 4, 24(1) # 8-byte Folded Reload1660; SPE-NEXT: li 5, 2561661; SPE-NEXT: evmergehi 3, 4, 41662; SPE-NEXT: evlddx 30, 1, 5 # 8-byte Folded Reload1663; SPE-NEXT: evldd 29, 248(1) # 8-byte Folded Reload1664; SPE-NEXT: evldd 28, 240(1) # 8-byte Folded Reload1665; SPE-NEXT: evldd 27, 232(1) # 8-byte Folded Reload1666; SPE-NEXT: evldd 26, 224(1) # 8-byte Folded Reload1667; SPE-NEXT: evldd 25, 216(1) # 8-byte Folded Reload1668; SPE-NEXT: evldd 24, 208(1) # 8-byte Folded Reload1669; SPE-NEXT: evldd 23, 200(1) # 8-byte Folded Reload1670; SPE-NEXT: evldd 22, 192(1) # 8-byte Folded Reload1671; SPE-NEXT: evldd 21, 184(1) # 8-byte Folded Reload1672; SPE-NEXT: evldd 20, 176(1) # 8-byte Folded Reload1673; SPE-NEXT: evldd 19, 168(1) # 8-byte Folded Reload1674; SPE-NEXT: evldd 18, 160(1) # 8-byte Folded Reload1675; SPE-NEXT: evldd 17, 152(1) # 8-byte Folded Reload1676; SPE-NEXT: evldd 16, 144(1) # 8-byte Folded Reload1677; SPE-NEXT: evldd 15, 136(1) # 8-byte Folded Reload1678; SPE-NEXT: evldd 14, 128(1) # 8-byte Folded Reload1679; SPE-NEXT: lwz 31, 284(1) # 4-byte Folded Reload1680; SPE-NEXT: lwz 0, 292(1)1681; SPE-NEXT: addi 1, 1, 2881682; SPE-NEXT: mtlr 01683; SPE-NEXT: blr1684;1685; EFPU2-LABEL: test_spill:1686; EFPU2: # %bb.0: # %entry1687; EFPU2-NEXT: mflr 01688; EFPU2-NEXT: stwu 1, -128(1)1689; EFPU2-NEXT: mr 5, 31690; EFPU2-NEXT: mr 6, 41691; EFPU2-NEXT: stw 0, 132(1)1692; EFPU2-NEXT: stw 27, 108(1) # 4-byte Folded Spill1693; EFPU2-NEXT: stw 28, 112(1) # 4-byte Folded Spill1694; EFPU2-NEXT: stw 29, 116(1) # 4-byte Folded Spill1695; EFPU2-NEXT: stw 30, 120(1) # 4-byte Folded Spill1696; EFPU2-NEXT: lwz 28, 136(1)1697; EFPU2-NEXT: bl __adddf31698; EFPU2-NEXT: lis 5, 163931699; EFPU2-NEXT: lis 6, -40691700; EFPU2-NEXT: ori 5, 5, 86971701; EFPU2-NEXT: ori 6, 6, 344141702; EFPU2-NEXT: #APP1703; EFPU2-NEXT: #NO_APP1704; EFPU2-NEXT: bl __adddf31705; EFPU2-NEXT: mr 30, 31706; EFPU2-NEXT: mr 29, 41707; EFPU2-NEXT: addi 3, 1, 561708; EFPU2-NEXT: li 4, 01709; EFPU2-NEXT: li 5, 241710; EFPU2-NEXT: li 6, 11711; EFPU2-NEXT: li 27, 01712; EFPU2-NEXT: bl test_memset1713; EFPU2-NEXT: stw 27, 0(28)1714; EFPU2-NEXT: bl test_func21715; EFPU2-NEXT: addi 3, 1, 121716; EFPU2-NEXT: li 4, 01717; EFPU2-NEXT: li 5, 201718; EFPU2-NEXT: li 6, 11719; EFPU2-NEXT: bl test_memset1720; EFPU2-NEXT: mr 3, 301721; EFPU2-NEXT: mr 4, 291722; EFPU2-NEXT: lwz 30, 120(1) # 4-byte Folded Reload1723; EFPU2-NEXT: lwz 29, 116(1) # 4-byte Folded Reload1724; EFPU2-NEXT: lwz 28, 112(1) # 4-byte Folded Reload1725; EFPU2-NEXT: lwz 27, 108(1) # 4-byte Folded Reload1726; EFPU2-NEXT: lwz 0, 132(1)1727; EFPU2-NEXT: addi 1, 1, 1281728; EFPU2-NEXT: mtlr 01729; EFPU2-NEXT: blr1730entry:1731 %v1 = alloca [13 x i32], align 41732 %v2 = alloca [11 x i32], align 41733 %0 = fadd double %a, %a1734 call void asm sideeffect "","~{s0},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind1735 %1 = fadd double %0, 3.141591736 call void @test_memset(ptr align 4 %v1, i8 0, i32 24, i1 true)1737 store i32 0, ptr %a5, align 41738 call void @test_func2()1739 call void @test_memset(ptr align 4 %v2, i8 0, i32 20, i1 true)1740 br label %return1741 1742return:1743 ret double %11744 1745}1746 1747define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 {1748; CHECK-LABEL: test_fma:1749; CHECK: # %bb.0: # %entry1750; CHECK-NEXT: mflr 01751; CHECK-NEXT: stwu 1, -32(1)1752; CHECK-NEXT: cmpwi 3, 01753; CHECK-NEXT: stw 0, 36(1)1754; CHECK-NEXT: stw 29, 20(1) # 4-byte Folded Spill1755; CHECK-NEXT: stw 30, 24(1) # 4-byte Folded Spill1756; CHECK-NEXT: ble 0, .LBB56_31757; CHECK-NEXT: # %bb.1: # %for.body.preheader1758; CHECK-NEXT: mr 30, 31759; CHECK-NEXT: li 29, 01760; CHECK-NEXT: # implicit-def: $r51761; CHECK-NEXT: .LBB56_2: # %for.body1762; CHECK-NEXT: #1763; CHECK-NEXT: efscfsi 3, 291764; CHECK-NEXT: mr 4, 31765; CHECK-NEXT: bl fmaf1766; CHECK-NEXT: addi 30, 30, -11767; CHECK-NEXT: mr 5, 31768; CHECK-NEXT: cmplwi 30, 01769; CHECK-NEXT: addi 29, 29, 11770; CHECK-NEXT: bc 12, 1, .LBB56_21771; CHECK-NEXT: b .LBB56_41772; CHECK-NEXT: .LBB56_3:1773; CHECK-NEXT: # implicit-def: $r51774; CHECK-NEXT: .LBB56_4: # %for.cond.cleanup1775; CHECK-NEXT: mr 3, 51776; CHECK-NEXT: lwz 30, 24(1) # 4-byte Folded Reload1777; CHECK-NEXT: lwz 29, 20(1) # 4-byte Folded Reload1778; CHECK-NEXT: lwz 0, 36(1)1779; CHECK-NEXT: addi 1, 1, 321780; CHECK-NEXT: mtlr 01781; CHECK-NEXT: blr1782entry:1783 %cmp8 = icmp sgt i32 %d, 01784 br i1 %cmp8, label %for.body, label %for.cond.cleanup1785 1786for.cond.cleanup: ; preds = %for.body, %entry1787 %e.0.lcssa = phi float [ undef, %entry ], [ %0, %for.body ]1788 ret float %e.0.lcssa1789 1790for.body: ; preds = %for.body, %entry1791 %f.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]1792 %e.09 = phi float [ %0, %for.body ], [ undef, %entry ]1793 %conv = sitofp i32 %f.010 to float1794 %0 = tail call float @llvm.fma.f32(float %conv, float %conv, float %e.09)1795 %inc = add nuw nsw i32 %f.010, 11796 %exitcond = icmp eq i32 %inc, %d1797 br i1 %exitcond, label %for.cond.cleanup, label %for.body1798}1799 1800; Function Attrs: nounwind readnone speculatable willreturn1801declare float @llvm.fma.f32(float, float, float) #11802 1803attributes #1 = { nounwind readnone speculatable willreturn }1804 1805%struct.a = type { float, float }1806 1807declare i32 @foo(double)1808 1809define void @d(ptr %e, ptr %f) #0 {1810; SPE-LABEL: d:1811; SPE: # %bb.0: # %entry1812; SPE-NEXT: mflr 01813; SPE-NEXT: stwu 1, -48(1)1814; SPE-NEXT: stw 0, 52(1)1815; SPE-NEXT: lwz 4, 0(4)1816; SPE-NEXT: lwz 3, 0(3)1817; SPE-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill1818; SPE-NEXT: efdcfs 29, 41819; SPE-NEXT: stw 28, 32(1) # 4-byte Folded Spill1820; SPE-NEXT: mr 4, 291821; SPE-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill1822; SPE-NEXT: efdcfs 30, 31823; SPE-NEXT: evmergehi 3, 29, 291824; SPE-NEXT: bl foo1825; SPE-NEXT: mr 28, 31826; SPE-NEXT: evmergehi 3, 30, 301827; SPE-NEXT: mr 4, 301828; SPE-NEXT: bl foo1829; SPE-NEXT: efdcfsi 3, 281830; SPE-NEXT: evldd 30, 16(1) # 8-byte Folded Reload1831; SPE-NEXT: efdmul 3, 29, 31832; SPE-NEXT: efscfd 3, 31833; SPE-NEXT: evldd 29, 8(1) # 8-byte Folded Reload1834; SPE-NEXT: stw 3, 0(3)1835; SPE-NEXT: lwz 28, 32(1) # 4-byte Folded Reload1836; SPE-NEXT: lwz 0, 52(1)1837; SPE-NEXT: addi 1, 1, 481838; SPE-NEXT: mtlr 01839; SPE-NEXT: blr1840;1841; EFPU2-LABEL: d:1842; EFPU2: # %bb.0: # %entry1843; EFPU2-NEXT: mflr 01844; EFPU2-NEXT: stwu 1, -32(1)1845; EFPU2-NEXT: stw 0, 36(1)1846; EFPU2-NEXT: lwz 3, 0(3)1847; EFPU2-NEXT: stw 26, 8(1) # 4-byte Folded Spill1848; EFPU2-NEXT: stw 27, 12(1) # 4-byte Folded Spill1849; EFPU2-NEXT: stw 28, 16(1) # 4-byte Folded Spill1850; EFPU2-NEXT: stw 29, 20(1) # 4-byte Folded Spill1851; EFPU2-NEXT: stw 30, 24(1) # 4-byte Folded Spill1852; EFPU2-NEXT: mr 30, 41853; EFPU2-NEXT: bl __extendsfdf21854; EFPU2-NEXT: mr 28, 31855; EFPU2-NEXT: lwz 3, 0(30)1856; EFPU2-NEXT: mr 29, 41857; EFPU2-NEXT: bl __extendsfdf21858; EFPU2-NEXT: mr 30, 41859; EFPU2-NEXT: mr 27, 31860; EFPU2-NEXT: bl foo1861; EFPU2-NEXT: mr 26, 31862; EFPU2-NEXT: mr 3, 281863; EFPU2-NEXT: mr 4, 291864; EFPU2-NEXT: bl foo1865; EFPU2-NEXT: mr 3, 261866; EFPU2-NEXT: bl __floatsidf1867; EFPU2-NEXT: mr 6, 41868; EFPU2-NEXT: mr 5, 31869; EFPU2-NEXT: mr 3, 271870; EFPU2-NEXT: mr 4, 301871; EFPU2-NEXT: bl __muldf31872; EFPU2-NEXT: bl __truncdfsf21873; EFPU2-NEXT: stw 3, 0(3)1874; EFPU2-NEXT: lwz 30, 24(1) # 4-byte Folded Reload1875; EFPU2-NEXT: lwz 29, 20(1) # 4-byte Folded Reload1876; EFPU2-NEXT: lwz 28, 16(1) # 4-byte Folded Reload1877; EFPU2-NEXT: lwz 27, 12(1) # 4-byte Folded Reload1878; EFPU2-NEXT: lwz 26, 8(1) # 4-byte Folded Reload1879; EFPU2-NEXT: lwz 0, 36(1)1880; EFPU2-NEXT: addi 1, 1, 321881; EFPU2-NEXT: mtlr 01882; EFPU2-NEXT: blr1883entry:1884 %0 = load float, ptr undef1885 %conv = fpext float %0 to double1886 %1 = load float, ptr %f1887 %g = fpext float %1 to double1888 %2 = call i32 @foo(double %g)1889 %h = call i32 @foo(double %conv)1890 %n = sitofp i32 %2 to double1891 %k = fmul double %g, %n1892 %l = fptrunc double %k to float1893 store float %l, ptr undef1894 ret void1895}1896attributes #0 = { nounwind }1897