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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-aix-xcoff \6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \7; RUN: FileCheck %s8; RUN: llc -verify-machineinstrs -mtriple=powerpc-aix-xcoff \9; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \10; RUN: FileCheck %s11 12define dso_local noundef <8 x i16> @v103s() local_unnamed_addr {13; CHECK-LABEL: v103s:14; CHECK: # %bb.0: # %entry15; CHECK-NEXT: xxspltib v2, 10316; CHECK-NEXT: vupklsb v2, v217; CHECK-NEXT: blr18entry:19 ret <8 x i16> splat (i16 103)20}21 22define dso_local noundef <2 x i64> @v103l() local_unnamed_addr {23; CHECK-LABEL: v103l:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: xxspltib v2, 10326; CHECK-NEXT: vextsb2d v2, v227; CHECK-NEXT: blr28entry:29 ret <2 x i64> splat (i64 103)30}31 32define dso_local noundef <4 x i32> @v103i() local_unnamed_addr {33; CHECK-LABEL: v103i:34; CHECK: # %bb.0: # %entry35; CHECK-NEXT: xxspltib v2, 10336; CHECK-NEXT: vextsb2w v2, v237; CHECK-NEXT: blr38entry:39 ret <4 x i32> splat (i32 103)40}41 42define dso_local noundef <2 x i64> @v11l() local_unnamed_addr {43; CHECK-LABEL: v11l:44; CHECK: # %bb.0: # %entry45; CHECK-NEXT: vspltisw v2, -1146; CHECK-NEXT: vupklsw v2, v247; CHECK-NEXT: blr48entry:49 ret <2 x i64> splat (i64 -11)50}51 52declare <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8>)53 54define i32 @crash(ptr %p) {55; CHECK-LABEL: crash:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: xxspltib v2, 12758; CHECK-NEXT: vextsb2w v2, v259; CHECK-NEXT: stxv v2, 0(r3)60; CHECK-NEXT: li r3, 061; CHECK-NEXT: stxv v2, 0(0)62; CHECK-NEXT: blr63entry:64 store <4 x i32> <i32 127, i32 127, i32 127, i32 127>, ptr %p, align 1665 %0 = call <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>)66 store <4 x i32> %0, ptr null, align 1667 ret i32 068}69