1009 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \3; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \4; RUN: -check-prefix=CHECK-LE %s5; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \6; RUN: -mtriple=powerpc64-linux-gnu -mcpu=ppc < %s | FileCheck \7; RUN: -check-prefix=CHECK-BE %s8; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \9; RUN: -mtriple=powerpc-linux-gnu < %s | FileCheck \10; RUN: -check-prefix=CHECK-32 %s11 12; Free probe13define i8 @f0() #0 nounwind {14; CHECK-LE-LABEL: f0:15; CHECK-LE: # %bb.0: # %entry16; CHECK-LE-NEXT: li r3, 317; CHECK-LE-NEXT: stb r3, -64(r1)18; CHECK-LE-NEXT: lbz r3, -64(r1)19; CHECK-LE-NEXT: blr20;21; CHECK-BE-LABEL: f0:22; CHECK-BE: # %bb.0: # %entry23; CHECK-BE-NEXT: li r3, 324; CHECK-BE-NEXT: stb r3, -64(r1)25; CHECK-BE-NEXT: lbz r3, -64(r1)26; CHECK-BE-NEXT: blr27;28; CHECK-32-LABEL: f0:29; CHECK-32: # %bb.0: # %entry30; CHECK-32-NEXT: stwu r1, -80(r1)31; CHECK-32-NEXT: li r3, 332; CHECK-32-NEXT: stb r3, 16(r1)33; CHECK-32-NEXT: lbz r3, 16(r1)34; CHECK-32-NEXT: addi r1, r1, 8035; CHECK-32-NEXT: blr36entry:37 %a = alloca i8, i64 6438 %b = getelementptr inbounds i8, ptr %a, i64 6339 store volatile i8 3, ptr %a40 %c = load volatile i8, ptr %a41 ret i8 %c42}43 44define i8 @f1() #0 "stack-probe-size"="0" {45; CHECK-LE-LABEL: f1:46; CHECK-LE: # %bb.0: # %entry47; CHECK-LE-NEXT: mr r0, r148; CHECK-LE-NEXT: .cfi_def_cfa r0, 049; CHECK-LE-NEXT: li r12, 25950; CHECK-LE-NEXT: mtctr r1251; CHECK-LE-NEXT: .LBB1_1: # %entry52; CHECK-LE-NEXT: #53; CHECK-LE-NEXT: stdu r0, -16(r1)54; CHECK-LE-NEXT: bdnz .LBB1_155; CHECK-LE-NEXT: # %bb.2: # %entry56; CHECK-LE-NEXT: .cfi_def_cfa_register r157; CHECK-LE-NEXT: .cfi_def_cfa_offset 414458; CHECK-LE-NEXT: li r3, 359; CHECK-LE-NEXT: stb r3, 48(r1)60; CHECK-LE-NEXT: lbz r3, 48(r1)61; CHECK-LE-NEXT: addi r1, r1, 414462; CHECK-LE-NEXT: blr63;64; CHECK-BE-LABEL: f1:65; CHECK-BE: # %bb.0: # %entry66; CHECK-BE-NEXT: mr r0, r167; CHECK-BE-NEXT: .cfi_def_cfa r0, 068; CHECK-BE-NEXT: li r12, 26069; CHECK-BE-NEXT: mtctr r1270; CHECK-BE-NEXT: .LBB1_1: # %entry71; CHECK-BE-NEXT: #72; CHECK-BE-NEXT: stdu r0, -16(r1)73; CHECK-BE-NEXT: bdnz .LBB1_174; CHECK-BE-NEXT: # %bb.2: # %entry75; CHECK-BE-NEXT: .cfi_def_cfa_register r176; CHECK-BE-NEXT: .cfi_def_cfa_offset 416077; CHECK-BE-NEXT: li r3, 378; CHECK-BE-NEXT: stb r3, 64(r1)79; CHECK-BE-NEXT: lbz r3, 64(r1)80; CHECK-BE-NEXT: addi r1, r1, 416081; CHECK-BE-NEXT: blr82;83; CHECK-32-LABEL: f1:84; CHECK-32: # %bb.0: # %entry85; CHECK-32-NEXT: mr r0, r186; CHECK-32-NEXT: .cfi_def_cfa r0, 087; CHECK-32-NEXT: li r12, 25788; CHECK-32-NEXT: mtctr r1289; CHECK-32-NEXT: .LBB1_1: # %entry90; CHECK-32-NEXT: #91; CHECK-32-NEXT: stwu r0, -16(r1)92; CHECK-32-NEXT: bdnz .LBB1_193; CHECK-32-NEXT: # %bb.2: # %entry94; CHECK-32-NEXT: .cfi_def_cfa_register r195; CHECK-32-NEXT: sub r0, r1, r096; CHECK-32-NEXT: sub r0, r1, r097; CHECK-32-NEXT: .cfi_def_cfa_offset 411298; CHECK-32-NEXT: li r3, 399; CHECK-32-NEXT: stb r3, 16(r1)100; CHECK-32-NEXT: lbz r3, 16(r1)101; CHECK-32-NEXT: addi r1, r1, 4112102; CHECK-32-NEXT: blr103entry:104 %a = alloca i8, i64 4096105 %b = getelementptr inbounds i8, ptr %a, i64 63106 store volatile i8 3, ptr %a107 %c = load volatile i8, ptr %a108 ret i8 %c109}110 111define i8 @f2() #0 {112; CHECK-LE-LABEL: f2:113; CHECK-LE: # %bb.0: # %entry114; CHECK-LE-NEXT: mr r0, r1115; CHECK-LE-NEXT: .cfi_def_cfa r0, 0116; CHECK-LE-NEXT: stdu r0, -48(r1)117; CHECK-LE-NEXT: li r12, 16118; CHECK-LE-NEXT: mtctr r12119; CHECK-LE-NEXT: .LBB2_1: # %entry120; CHECK-LE-NEXT: #121; CHECK-LE-NEXT: stdu r0, -4096(r1)122; CHECK-LE-NEXT: bdnz .LBB2_1123; CHECK-LE-NEXT: # %bb.2: # %entry124; CHECK-LE-NEXT: .cfi_def_cfa_register r1125; CHECK-LE-NEXT: .cfi_def_cfa_offset 65584126; CHECK-LE-NEXT: li r3, 3127; CHECK-LE-NEXT: stb r3, 48(r1)128; CHECK-LE-NEXT: lbz r3, 48(r1)129; CHECK-LE-NEXT: ld r1, 0(r1)130; CHECK-LE-NEXT: blr131;132; CHECK-BE-LABEL: f2:133; CHECK-BE: # %bb.0: # %entry134; CHECK-BE-NEXT: mr r0, r1135; CHECK-BE-NEXT: .cfi_def_cfa r0, 0136; CHECK-BE-NEXT: stdu r0, -64(r1)137; CHECK-BE-NEXT: li r12, 16138; CHECK-BE-NEXT: mtctr r12139; CHECK-BE-NEXT: .LBB2_1: # %entry140; CHECK-BE-NEXT: #141; CHECK-BE-NEXT: stdu r0, -4096(r1)142; CHECK-BE-NEXT: bdnz .LBB2_1143; CHECK-BE-NEXT: # %bb.2: # %entry144; CHECK-BE-NEXT: .cfi_def_cfa_register r1145; CHECK-BE-NEXT: .cfi_def_cfa_offset 65600146; CHECK-BE-NEXT: li r3, 3147; CHECK-BE-NEXT: stb r3, 64(r1)148; CHECK-BE-NEXT: lbz r3, 64(r1)149; CHECK-BE-NEXT: ld r1, 0(r1)150; CHECK-BE-NEXT: blr151;152; CHECK-32-LABEL: f2:153; CHECK-32: # %bb.0: # %entry154; CHECK-32-NEXT: mr r0, r1155; CHECK-32-NEXT: .cfi_def_cfa r0, 0156; CHECK-32-NEXT: stwu r0, -16(r1)157; CHECK-32-NEXT: li r12, 16158; CHECK-32-NEXT: mtctr r12159; CHECK-32-NEXT: .LBB2_1: # %entry160; CHECK-32-NEXT: #161; CHECK-32-NEXT: stwu r0, -4096(r1)162; CHECK-32-NEXT: bdnz .LBB2_1163; CHECK-32-NEXT: # %bb.2: # %entry164; CHECK-32-NEXT: .cfi_def_cfa_register r1165; CHECK-32-NEXT: sub r0, r1, r0166; CHECK-32-NEXT: sub r0, r1, r0167; CHECK-32-NEXT: .cfi_def_cfa_offset 65552168; CHECK-32-NEXT: li r3, 3169; CHECK-32-NEXT: stb r3, 16(r1)170; CHECK-32-NEXT: mr r0, r31171; CHECK-32-NEXT: lbz r3, 16(r1)172; CHECK-32-NEXT: lwz r31, 0(r1)173; CHECK-32-NEXT: mr r1, r31174; CHECK-32-NEXT: mr r31, r0175; CHECK-32-NEXT: blr176entry:177 %a = alloca i8, i64 65536178 %b = getelementptr inbounds i8, ptr %a, i64 63179 store volatile i8 3, ptr %a180 %c = load volatile i8, ptr %a181 ret i8 %c182}183 184define i8 @f3() #0 "stack-probe-size"="32768" {185; CHECK-LE-LABEL: f3:186; CHECK-LE: # %bb.0: # %entry187; CHECK-LE-NEXT: mr r0, r1188; CHECK-LE-NEXT: .cfi_def_cfa r0, 0189; CHECK-LE-NEXT: stdu r0, -48(r1)190; CHECK-LE-NEXT: stdu r0, -32768(r1)191; CHECK-LE-NEXT: stdu r0, -32768(r1)192; CHECK-LE-NEXT: .cfi_def_cfa_register r1193; CHECK-LE-NEXT: .cfi_def_cfa_offset 65584194; CHECK-LE-NEXT: li r3, 3195; CHECK-LE-NEXT: stb r3, 48(r1)196; CHECK-LE-NEXT: lbz r3, 48(r1)197; CHECK-LE-NEXT: ld r1, 0(r1)198; CHECK-LE-NEXT: blr199;200; CHECK-BE-LABEL: f3:201; CHECK-BE: # %bb.0: # %entry202; CHECK-BE-NEXT: mr r0, r1203; CHECK-BE-NEXT: .cfi_def_cfa r0, 0204; CHECK-BE-NEXT: stdu r0, -64(r1)205; CHECK-BE-NEXT: stdu r0, -32768(r1)206; CHECK-BE-NEXT: stdu r0, -32768(r1)207; CHECK-BE-NEXT: .cfi_def_cfa_register r1208; CHECK-BE-NEXT: .cfi_def_cfa_offset 65600209; CHECK-BE-NEXT: li r3, 3210; CHECK-BE-NEXT: stb r3, 64(r1)211; CHECK-BE-NEXT: lbz r3, 64(r1)212; CHECK-BE-NEXT: ld r1, 0(r1)213; CHECK-BE-NEXT: blr214;215; CHECK-32-LABEL: f3:216; CHECK-32: # %bb.0: # %entry217; CHECK-32-NEXT: mr r0, r1218; CHECK-32-NEXT: .cfi_def_cfa r0, 0219; CHECK-32-NEXT: stwu r0, -16(r1)220; CHECK-32-NEXT: stwu r0, -32768(r1)221; CHECK-32-NEXT: stwu r0, -32768(r1)222; CHECK-32-NEXT: .cfi_def_cfa_register r1223; CHECK-32-NEXT: sub r0, r1, r0224; CHECK-32-NEXT: sub r0, r1, r0225; CHECK-32-NEXT: .cfi_def_cfa_offset 65552226; CHECK-32-NEXT: li r3, 3227; CHECK-32-NEXT: stb r3, 16(r1)228; CHECK-32-NEXT: mr r0, r31229; CHECK-32-NEXT: lbz r3, 16(r1)230; CHECK-32-NEXT: lwz r31, 0(r1)231; CHECK-32-NEXT: mr r1, r31232; CHECK-32-NEXT: mr r31, r0233; CHECK-32-NEXT: blr234entry:235 %a = alloca i8, i64 65536236 %b = getelementptr inbounds i8, ptr %a, i64 63237 store volatile i8 3, ptr %a238 %c = load volatile i8, ptr %a239 ret i8 %c240}241 242; Same as f2, but without protection.243define i8 @f4() {244; CHECK-LE-LABEL: f4:245; CHECK-LE: # %bb.0: # %entry246; CHECK-LE-NEXT: lis r0, -2247; CHECK-LE-NEXT: ori r0, r0, 65488248; CHECK-LE-NEXT: stdux r1, r1, r0249; CHECK-LE-NEXT: .cfi_def_cfa_offset 65584250; CHECK-LE-NEXT: li r3, 3251; CHECK-LE-NEXT: stb r3, 48(r1)252; CHECK-LE-NEXT: lbz r3, 48(r1)253; CHECK-LE-NEXT: ld r1, 0(r1)254; CHECK-LE-NEXT: blr255;256; CHECK-BE-LABEL: f4:257; CHECK-BE: # %bb.0: # %entry258; CHECK-BE-NEXT: lis r0, -2259; CHECK-BE-NEXT: ori r0, r0, 65472260; CHECK-BE-NEXT: stdux r1, r1, r0261; CHECK-BE-NEXT: .cfi_def_cfa_offset 65600262; CHECK-BE-NEXT: li r3, 3263; CHECK-BE-NEXT: stb r3, 64(r1)264; CHECK-BE-NEXT: lbz r3, 64(r1)265; CHECK-BE-NEXT: ld r1, 0(r1)266; CHECK-BE-NEXT: blr267;268; CHECK-32-LABEL: f4:269; CHECK-32: # %bb.0: # %entry270; CHECK-32-NEXT: lis r0, -2271; CHECK-32-NEXT: ori r0, r0, 65520272; CHECK-32-NEXT: stwux r1, r1, r0273; CHECK-32-NEXT: sub r0, r1, r0274; CHECK-32-NEXT: .cfi_def_cfa_offset 65552275; CHECK-32-NEXT: li r3, 3276; CHECK-32-NEXT: stb r3, 16(r1)277; CHECK-32-NEXT: mr r0, r31278; CHECK-32-NEXT: lbz r3, 16(r1)279; CHECK-32-NEXT: lwz r31, 0(r1)280; CHECK-32-NEXT: mr r1, r31281; CHECK-32-NEXT: mr r31, r0282; CHECK-32-NEXT: blr283entry:284 %a = alloca i8, i64 65536285 %b = getelementptr inbounds i8, ptr %a, i64 63286 store volatile i8 3, ptr %a287 %c = load volatile i8, ptr %a288 ret i8 %c289}290 291define i8 @f5() #0 "stack-probe-size"="65536" {292; CHECK-LE-LABEL: f5:293; CHECK-LE: # %bb.0: # %entry294; CHECK-LE-NEXT: mr r0, r1295; CHECK-LE-NEXT: .cfi_def_cfa r0, 0296; CHECK-LE-NEXT: stdu r0, -48(r1)297; CHECK-LE-NEXT: li r12, 16298; CHECK-LE-NEXT: mtctr r12299; CHECK-LE-NEXT: lis r12, -1300; CHECK-LE-NEXT: ori r12, r12, 0301; CHECK-LE-NEXT: .LBB5_1: # %entry302; CHECK-LE-NEXT: #303; CHECK-LE-NEXT: stdux r0, r1, r12304; CHECK-LE-NEXT: bdnz .LBB5_1305; CHECK-LE-NEXT: # %bb.2: # %entry306; CHECK-LE-NEXT: .cfi_def_cfa_register r1307; CHECK-LE-NEXT: .cfi_def_cfa_offset 1048624308; CHECK-LE-NEXT: li r3, 3309; CHECK-LE-NEXT: stb r3, 48(r1)310; CHECK-LE-NEXT: lbz r3, 48(r1)311; CHECK-LE-NEXT: ld r1, 0(r1)312; CHECK-LE-NEXT: blr313;314; CHECK-BE-LABEL: f5:315; CHECK-BE: # %bb.0: # %entry316; CHECK-BE-NEXT: mr r0, r1317; CHECK-BE-NEXT: .cfi_def_cfa r0, 0318; CHECK-BE-NEXT: stdu r0, -64(r1)319; CHECK-BE-NEXT: li r12, 16320; CHECK-BE-NEXT: mtctr r12321; CHECK-BE-NEXT: lis r12, -1322; CHECK-BE-NEXT: ori r12, r12, 0323; CHECK-BE-NEXT: .LBB5_1: # %entry324; CHECK-BE-NEXT: #325; CHECK-BE-NEXT: stdux r0, r1, r12326; CHECK-BE-NEXT: bdnz .LBB5_1327; CHECK-BE-NEXT: # %bb.2: # %entry328; CHECK-BE-NEXT: .cfi_def_cfa_register r1329; CHECK-BE-NEXT: .cfi_def_cfa_offset 1048640330; CHECK-BE-NEXT: li r3, 3331; CHECK-BE-NEXT: stb r3, 64(r1)332; CHECK-BE-NEXT: lbz r3, 64(r1)333; CHECK-BE-NEXT: ld r1, 0(r1)334; CHECK-BE-NEXT: blr335;336; CHECK-32-LABEL: f5:337; CHECK-32: # %bb.0: # %entry338; CHECK-32-NEXT: mr r0, r1339; CHECK-32-NEXT: .cfi_def_cfa r0, 0340; CHECK-32-NEXT: stwu r0, -16(r1)341; CHECK-32-NEXT: li r12, 16342; CHECK-32-NEXT: mtctr r12343; CHECK-32-NEXT: lis r12, -1344; CHECK-32-NEXT: ori r12, r12, 0345; CHECK-32-NEXT: .LBB5_1: # %entry346; CHECK-32-NEXT: #347; CHECK-32-NEXT: stwux r0, r1, r12348; CHECK-32-NEXT: bdnz .LBB5_1349; CHECK-32-NEXT: # %bb.2: # %entry350; CHECK-32-NEXT: .cfi_def_cfa_register r1351; CHECK-32-NEXT: sub r0, r1, r0352; CHECK-32-NEXT: sub r0, r1, r0353; CHECK-32-NEXT: .cfi_def_cfa_offset 1048592354; CHECK-32-NEXT: li r3, 3355; CHECK-32-NEXT: stb r3, 16(r1)356; CHECK-32-NEXT: mr r0, r31357; CHECK-32-NEXT: lbz r3, 16(r1)358; CHECK-32-NEXT: lwz r31, 0(r1)359; CHECK-32-NEXT: mr r1, r31360; CHECK-32-NEXT: mr r31, r0361; CHECK-32-NEXT: blr362entry:363 %a = alloca i8, i64 1048576364 %b = getelementptr inbounds i8, ptr %a, i64 63365 store volatile i8 3, ptr %a366 %c = load volatile i8, ptr %a367 ret i8 %c368}369 370define i8 @f6() #0 {371; CHECK-LE-LABEL: f6:372; CHECK-LE: # %bb.0: # %entry373; CHECK-LE-NEXT: mr r0, r1374; CHECK-LE-NEXT: .cfi_def_cfa r0, 0375; CHECK-LE-NEXT: stdu r0, -48(r1)376; CHECK-LE-NEXT: lis r12, 4377; CHECK-LE-NEXT: ori r12, r12, 0378; CHECK-LE-NEXT: mtctr r12379; CHECK-LE-NEXT: .LBB6_1: # %entry380; CHECK-LE-NEXT: #381; CHECK-LE-NEXT: stdu r0, -4096(r1)382; CHECK-LE-NEXT: bdnz .LBB6_1383; CHECK-LE-NEXT: # %bb.2: # %entry384; CHECK-LE-NEXT: .cfi_def_cfa_register r1385; CHECK-LE-NEXT: .cfi_def_cfa_offset 1073741872386; CHECK-LE-NEXT: li r3, 3387; CHECK-LE-NEXT: stb r3, 48(r1)388; CHECK-LE-NEXT: lbz r3, 48(r1)389; CHECK-LE-NEXT: ld r1, 0(r1)390; CHECK-LE-NEXT: blr391;392; CHECK-BE-LABEL: f6:393; CHECK-BE: # %bb.0: # %entry394; CHECK-BE-NEXT: mr r0, r1395; CHECK-BE-NEXT: .cfi_def_cfa r0, 0396; CHECK-BE-NEXT: stdu r0, -64(r1)397; CHECK-BE-NEXT: lis r12, 4398; CHECK-BE-NEXT: ori r12, r12, 0399; CHECK-BE-NEXT: mtctr r12400; CHECK-BE-NEXT: .LBB6_1: # %entry401; CHECK-BE-NEXT: #402; CHECK-BE-NEXT: stdu r0, -4096(r1)403; CHECK-BE-NEXT: bdnz .LBB6_1404; CHECK-BE-NEXT: # %bb.2: # %entry405; CHECK-BE-NEXT: .cfi_def_cfa_register r1406; CHECK-BE-NEXT: .cfi_def_cfa_offset 1073741888407; CHECK-BE-NEXT: li r3, 3408; CHECK-BE-NEXT: stb r3, 64(r1)409; CHECK-BE-NEXT: lbz r3, 64(r1)410; CHECK-BE-NEXT: ld r1, 0(r1)411; CHECK-BE-NEXT: blr412;413; CHECK-32-LABEL: f6:414; CHECK-32: # %bb.0: # %entry415; CHECK-32-NEXT: mr r0, r1416; CHECK-32-NEXT: .cfi_def_cfa r0, 0417; CHECK-32-NEXT: stwu r0, -16(r1)418; CHECK-32-NEXT: lis r12, 4419; CHECK-32-NEXT: ori r12, r12, 0420; CHECK-32-NEXT: mtctr r12421; CHECK-32-NEXT: .LBB6_1: # %entry422; CHECK-32-NEXT: #423; CHECK-32-NEXT: stwu r0, -4096(r1)424; CHECK-32-NEXT: bdnz .LBB6_1425; CHECK-32-NEXT: # %bb.2: # %entry426; CHECK-32-NEXT: .cfi_def_cfa_register r1427; CHECK-32-NEXT: sub r0, r1, r0428; CHECK-32-NEXT: sub r0, r1, r0429; CHECK-32-NEXT: .cfi_def_cfa_offset 1073741840430; CHECK-32-NEXT: li r3, 3431; CHECK-32-NEXT: stb r3, 16(r1)432; CHECK-32-NEXT: mr r0, r31433; CHECK-32-NEXT: lbz r3, 16(r1)434; CHECK-32-NEXT: lwz r31, 0(r1)435; CHECK-32-NEXT: mr r1, r31436; CHECK-32-NEXT: mr r31, r0437; CHECK-32-NEXT: blr438entry:439 %a = alloca i8, i64 1073741824440 %b = getelementptr inbounds i8, ptr %a, i64 63441 store volatile i8 3, ptr %a442 %c = load volatile i8, ptr %a443 ret i8 %c444}445 446define i8 @f7() #0 "stack-probe-size"="65536" {447; CHECK-LE-LABEL: f7:448; CHECK-LE: # %bb.0: # %entry449; CHECK-LE-NEXT: mr r0, r1450; CHECK-LE-NEXT: .cfi_def_cfa r0, 0451; CHECK-LE-NEXT: lis r12, -1452; CHECK-LE-NEXT: ori r12, r12, 13776453; CHECK-LE-NEXT: stdux r0, r1, r12454; CHECK-LE-NEXT: li r12, 15258455; CHECK-LE-NEXT: mtctr r12456; CHECK-LE-NEXT: lis r12, -1457; CHECK-LE-NEXT: ori r12, r12, 0458; CHECK-LE-NEXT: .LBB7_1: # %entry459; CHECK-LE-NEXT: #460; CHECK-LE-NEXT: stdux r0, r1, r12461; CHECK-LE-NEXT: bdnz .LBB7_1462; CHECK-LE-NEXT: # %bb.2: # %entry463; CHECK-LE-NEXT: .cfi_def_cfa_register r1464; CHECK-LE-NEXT: .cfi_def_cfa_offset 1000000048465; CHECK-LE-NEXT: li r3, 3466; CHECK-LE-NEXT: stb r3, 41(r1)467; CHECK-LE-NEXT: lbz r3, 41(r1)468; CHECK-LE-NEXT: ld r1, 0(r1)469; CHECK-LE-NEXT: blr470;471; CHECK-BE-LABEL: f7:472; CHECK-BE: # %bb.0: # %entry473; CHECK-BE-NEXT: mr r0, r1474; CHECK-BE-NEXT: .cfi_def_cfa r0, 0475; CHECK-BE-NEXT: lis r12, -1476; CHECK-BE-NEXT: ori r12, r12, 13760477; CHECK-BE-NEXT: stdux r0, r1, r12478; CHECK-BE-NEXT: li r12, 15258479; CHECK-BE-NEXT: mtctr r12480; CHECK-BE-NEXT: lis r12, -1481; CHECK-BE-NEXT: ori r12, r12, 0482; CHECK-BE-NEXT: .LBB7_1: # %entry483; CHECK-BE-NEXT: #484; CHECK-BE-NEXT: stdux r0, r1, r12485; CHECK-BE-NEXT: bdnz .LBB7_1486; CHECK-BE-NEXT: # %bb.2: # %entry487; CHECK-BE-NEXT: .cfi_def_cfa_register r1488; CHECK-BE-NEXT: .cfi_def_cfa_offset 1000000064489; CHECK-BE-NEXT: li r3, 3490; CHECK-BE-NEXT: stb r3, 57(r1)491; CHECK-BE-NEXT: lbz r3, 57(r1)492; CHECK-BE-NEXT: ld r1, 0(r1)493; CHECK-BE-NEXT: blr494;495; CHECK-32-LABEL: f7:496; CHECK-32: # %bb.0: # %entry497; CHECK-32-NEXT: mr r0, r1498; CHECK-32-NEXT: .cfi_def_cfa r0, 0499; CHECK-32-NEXT: lis r12, -1500; CHECK-32-NEXT: ori r12, r12, 13808501; CHECK-32-NEXT: stwux r0, r1, r12502; CHECK-32-NEXT: li r12, 15258503; CHECK-32-NEXT: mtctr r12504; CHECK-32-NEXT: lis r12, -1505; CHECK-32-NEXT: ori r12, r12, 0506; CHECK-32-NEXT: .LBB7_1: # %entry507; CHECK-32-NEXT: #508; CHECK-32-NEXT: stwux r0, r1, r12509; CHECK-32-NEXT: bdnz .LBB7_1510; CHECK-32-NEXT: # %bb.2: # %entry511; CHECK-32-NEXT: .cfi_def_cfa_register r1512; CHECK-32-NEXT: sub r0, r1, r0513; CHECK-32-NEXT: sub r0, r1, r0514; CHECK-32-NEXT: .cfi_def_cfa_offset 1000000016515; CHECK-32-NEXT: li r3, 3516; CHECK-32-NEXT: stb r3, 9(r1)517; CHECK-32-NEXT: mr r0, r31518; CHECK-32-NEXT: lbz r3, 9(r1)519; CHECK-32-NEXT: lwz r31, 0(r1)520; CHECK-32-NEXT: mr r1, r31521; CHECK-32-NEXT: mr r31, r0522; CHECK-32-NEXT: blr523entry:524 %a = alloca i8, i64 1000000007525 %b = getelementptr inbounds i8, ptr %a, i64 101526 store volatile i8 3, ptr %a527 %c = load volatile i8, ptr %a528 ret i8 %c529}530 531; alloca + align < probe_size532define i32 @f8(i64 %i) local_unnamed_addr #0 {533; CHECK-LE-LABEL: f8:534; CHECK-LE: # %bb.0:535; CHECK-LE-NEXT: clrldi r0, r1, 58536; CHECK-LE-NEXT: std r30, -16(r1)537; CHECK-LE-NEXT: mr r30, r1538; CHECK-LE-NEXT: subfic r0, r0, -896539; CHECK-LE-NEXT: stdux r1, r1, r0540; CHECK-LE-NEXT: .cfi_def_cfa_register r30541; CHECK-LE-NEXT: .cfi_offset r30, -16542; CHECK-LE-NEXT: sldi r3, r3, 2543; CHECK-LE-NEXT: addi r4, r1, 64544; CHECK-LE-NEXT: li r5, 1545; CHECK-LE-NEXT: stwx r5, r4, r3546; CHECK-LE-NEXT: lwz r3, 64(r1)547; CHECK-LE-NEXT: mr r1, r30548; CHECK-LE-NEXT: ld r30, -16(r1)549; CHECK-LE-NEXT: blr550;551; CHECK-BE-LABEL: f8:552; CHECK-BE: # %bb.0:553; CHECK-BE-NEXT: clrldi r0, r1, 58554; CHECK-BE-NEXT: std r30, -16(r1)555; CHECK-BE-NEXT: mr r30, r1556; CHECK-BE-NEXT: subfic r0, r0, -896557; CHECK-BE-NEXT: stdux r1, r1, r0558; CHECK-BE-NEXT: .cfi_def_cfa_register r30559; CHECK-BE-NEXT: .cfi_offset r30, -16560; CHECK-BE-NEXT: addi r4, r1, 64561; CHECK-BE-NEXT: li r5, 1562; CHECK-BE-NEXT: sldi r3, r3, 2563; CHECK-BE-NEXT: stwx r5, r4, r3564; CHECK-BE-NEXT: lwz r3, 64(r1)565; CHECK-BE-NEXT: mr r1, r30566; CHECK-BE-NEXT: ld r30, -16(r1)567; CHECK-BE-NEXT: blr568;569; CHECK-32-LABEL: f8:570; CHECK-32: # %bb.0:571; CHECK-32-NEXT: clrlwi r0, r1, 26572; CHECK-32-NEXT: subfic r0, r0, -896573; CHECK-32-NEXT: stwux r1, r1, r0574; CHECK-32-NEXT: sub r0, r1, r0575; CHECK-32-NEXT: addic r0, r0, -8576; CHECK-32-NEXT: stwx r30, 0, r0577; CHECK-32-NEXT: addic r30, r0, 8578; CHECK-32-NEXT: .cfi_def_cfa_register r30579; CHECK-32-NEXT: .cfi_offset r30, -8580; CHECK-32-NEXT: addi r3, r1, 64581; CHECK-32-NEXT: li r5, 1582; CHECK-32-NEXT: slwi r4, r4, 2583; CHECK-32-NEXT: stwx r5, r3, r4584; CHECK-32-NEXT: mr r0, r31585; CHECK-32-NEXT: lwz r3, 64(r1)586; CHECK-32-NEXT: lwz r31, 0(r1)587; CHECK-32-NEXT: lwz r30, -8(r31)588; CHECK-32-NEXT: mr r1, r31589; CHECK-32-NEXT: mr r31, r0590; CHECK-32-NEXT: blr591 %a = alloca i32, i32 200, align 64592 %b = getelementptr inbounds i32, ptr %a, i64 %i593 store volatile i32 1, ptr %b594 %c = load volatile i32, ptr %a595 ret i32 %c596}597 598; alloca > probe_size, align > probe_size599define i32 @f9(i64 %i) local_unnamed_addr #0 {600; CHECK-LE-LABEL: f9:601; CHECK-LE: # %bb.0:602; CHECK-LE-NEXT: clrldi r12, r1, 53603; CHECK-LE-NEXT: std r30, -16(r1)604; CHECK-LE-NEXT: mr r30, r1605; CHECK-LE-NEXT: sub r0, r1, r12606; CHECK-LE-NEXT: li r12, -10240607; CHECK-LE-NEXT: add r0, r12, r0608; CHECK-LE-NEXT: sub r12, r0, r1609; CHECK-LE-NEXT: cmpdi r12, -4096610; CHECK-LE-NEXT: bge cr0, .LBB9_2611; CHECK-LE-NEXT: .LBB9_1:612; CHECK-LE-NEXT: stdu r30, -4096(r1)613; CHECK-LE-NEXT: addi r12, r12, 4096614; CHECK-LE-NEXT: cmpdi r12, -4096615; CHECK-LE-NEXT: blt cr0, .LBB9_1616; CHECK-LE-NEXT: .LBB9_2:617; CHECK-LE-NEXT: stdux r30, r1, r12618; CHECK-LE-NEXT: mr r0, r30619; CHECK-LE-NEXT: .cfi_def_cfa_register r0620; CHECK-LE-NEXT: .cfi_def_cfa_register r30621; CHECK-LE-NEXT: .cfi_offset r30, -16622; CHECK-LE-NEXT: sldi r3, r3, 2623; CHECK-LE-NEXT: addi r4, r1, 2048624; CHECK-LE-NEXT: li r5, 1625; CHECK-LE-NEXT: stwx r5, r4, r3626; CHECK-LE-NEXT: lwz r3, 2048(r1)627; CHECK-LE-NEXT: mr r1, r30628; CHECK-LE-NEXT: ld r30, -16(r1)629; CHECK-LE-NEXT: blr630;631; CHECK-BE-LABEL: f9:632; CHECK-BE: # %bb.0:633; CHECK-BE-NEXT: clrldi r12, r1, 53634; CHECK-BE-NEXT: std r30, -16(r1)635; CHECK-BE-NEXT: mr r30, r1636; CHECK-BE-NEXT: sub r0, r1, r12637; CHECK-BE-NEXT: li r12, -10240638; CHECK-BE-NEXT: add r0, r12, r0639; CHECK-BE-NEXT: sub r12, r0, r1640; CHECK-BE-NEXT: cmpdi r12, -4096641; CHECK-BE-NEXT: bge cr0, .LBB9_2642; CHECK-BE-NEXT: .LBB9_1:643; CHECK-BE-NEXT: stdu r30, -4096(r1)644; CHECK-BE-NEXT: addi r12, r12, 4096645; CHECK-BE-NEXT: cmpdi r12, -4096646; CHECK-BE-NEXT: blt cr0, .LBB9_1647; CHECK-BE-NEXT: .LBB9_2:648; CHECK-BE-NEXT: stdux r30, r1, r12649; CHECK-BE-NEXT: mr r0, r30650; CHECK-BE-NEXT: .cfi_def_cfa_register r0651; CHECK-BE-NEXT: .cfi_def_cfa_register r30652; CHECK-BE-NEXT: .cfi_offset r30, -16653; CHECK-BE-NEXT: addi r4, r1, 2048654; CHECK-BE-NEXT: li r5, 1655; CHECK-BE-NEXT: sldi r3, r3, 2656; CHECK-BE-NEXT: stwx r5, r4, r3657; CHECK-BE-NEXT: lwz r3, 2048(r1)658; CHECK-BE-NEXT: mr r1, r30659; CHECK-BE-NEXT: ld r30, -16(r1)660; CHECK-BE-NEXT: blr661;662; CHECK-32-LABEL: f9:663; CHECK-32: # %bb.0:664; CHECK-32-NEXT: clrlwi r12, r1, 21665; CHECK-32-NEXT: sub r0, r1, r12666; CHECK-32-NEXT: li r12, -10240667; CHECK-32-NEXT: add r0, r12, r0668; CHECK-32-NEXT: sub r12, r0, r1669; CHECK-32-NEXT: mr r0, r1670; CHECK-32-NEXT: cmpwi r12, -4096671; CHECK-32-NEXT: bge cr0, .LBB9_2672; CHECK-32-NEXT: .LBB9_1:673; CHECK-32-NEXT: stwu r0, -4096(r1)674; CHECK-32-NEXT: addi r12, r12, 4096675; CHECK-32-NEXT: cmpwi r12, -4096676; CHECK-32-NEXT: blt cr0, .LBB9_1677; CHECK-32-NEXT: .LBB9_2:678; CHECK-32-NEXT: stwux r0, r1, r12679; CHECK-32-NEXT: .cfi_def_cfa_register r0680; CHECK-32-NEXT: sub r0, r1, r0681; CHECK-32-NEXT: sub r0, r1, r0682; CHECK-32-NEXT: addic r0, r0, -8683; CHECK-32-NEXT: stwx r30, 0, r0684; CHECK-32-NEXT: addic r30, r0, 8685; CHECK-32-NEXT: .cfi_def_cfa_register r30686; CHECK-32-NEXT: .cfi_offset r30, -8687; CHECK-32-NEXT: addi r3, r1, 2048688; CHECK-32-NEXT: li r5, 1689; CHECK-32-NEXT: slwi r4, r4, 2690; CHECK-32-NEXT: stwx r5, r3, r4691; CHECK-32-NEXT: mr r0, r31692; CHECK-32-NEXT: lwz r3, 2048(r1)693; CHECK-32-NEXT: lwz r31, 0(r1)694; CHECK-32-NEXT: lwz r30, -8(r31)695; CHECK-32-NEXT: mr r1, r31696; CHECK-32-NEXT: mr r31, r0697; CHECK-32-NEXT: blr698 %a = alloca i32, i32 2000, align 2048699 %b = getelementptr inbounds i32, ptr %a, i64 %i700 store volatile i32 1, ptr %b701 %c = load volatile i32, ptr %a702 ret i32 %c703}704 705; alloca < probe_size, align < probe_size, alloca + align > probe_size706define i32 @f10(i64 %i) local_unnamed_addr #0 {707; CHECK-LE-LABEL: f10:708; CHECK-LE: # %bb.0:709; CHECK-LE-NEXT: clrldi r12, r1, 54710; CHECK-LE-NEXT: std r30, -16(r1)711; CHECK-LE-NEXT: mr r30, r1712; CHECK-LE-NEXT: sub r0, r1, r12713; CHECK-LE-NEXT: li r12, -5120714; CHECK-LE-NEXT: add r0, r12, r0715; CHECK-LE-NEXT: sub r12, r0, r1716; CHECK-LE-NEXT: cmpdi r12, -4096717; CHECK-LE-NEXT: bge cr0, .LBB10_2718; CHECK-LE-NEXT: .LBB10_1:719; CHECK-LE-NEXT: stdu r30, -4096(r1)720; CHECK-LE-NEXT: addi r12, r12, 4096721; CHECK-LE-NEXT: cmpdi r12, -4096722; CHECK-LE-NEXT: blt cr0, .LBB10_1723; CHECK-LE-NEXT: .LBB10_2:724; CHECK-LE-NEXT: stdux r30, r1, r12725; CHECK-LE-NEXT: mr r0, r30726; CHECK-LE-NEXT: .cfi_def_cfa_register r0727; CHECK-LE-NEXT: .cfi_def_cfa_register r30728; CHECK-LE-NEXT: .cfi_offset r30, -16729; CHECK-LE-NEXT: sldi r3, r3, 2730; CHECK-LE-NEXT: addi r4, r1, 1024731; CHECK-LE-NEXT: li r5, 1732; CHECK-LE-NEXT: stwx r5, r4, r3733; CHECK-LE-NEXT: lwz r3, 1024(r1)734; CHECK-LE-NEXT: mr r1, r30735; CHECK-LE-NEXT: ld r30, -16(r1)736; CHECK-LE-NEXT: blr737;738; CHECK-BE-LABEL: f10:739; CHECK-BE: # %bb.0:740; CHECK-BE-NEXT: clrldi r12, r1, 54741; CHECK-BE-NEXT: std r30, -16(r1)742; CHECK-BE-NEXT: mr r30, r1743; CHECK-BE-NEXT: sub r0, r1, r12744; CHECK-BE-NEXT: li r12, -5120745; CHECK-BE-NEXT: add r0, r12, r0746; CHECK-BE-NEXT: sub r12, r0, r1747; CHECK-BE-NEXT: cmpdi r12, -4096748; CHECK-BE-NEXT: bge cr0, .LBB10_2749; CHECK-BE-NEXT: .LBB10_1:750; CHECK-BE-NEXT: stdu r30, -4096(r1)751; CHECK-BE-NEXT: addi r12, r12, 4096752; CHECK-BE-NEXT: cmpdi r12, -4096753; CHECK-BE-NEXT: blt cr0, .LBB10_1754; CHECK-BE-NEXT: .LBB10_2:755; CHECK-BE-NEXT: stdux r30, r1, r12756; CHECK-BE-NEXT: mr r0, r30757; CHECK-BE-NEXT: .cfi_def_cfa_register r0758; CHECK-BE-NEXT: .cfi_def_cfa_register r30759; CHECK-BE-NEXT: .cfi_offset r30, -16760; CHECK-BE-NEXT: addi r4, r1, 1024761; CHECK-BE-NEXT: li r5, 1762; CHECK-BE-NEXT: sldi r3, r3, 2763; CHECK-BE-NEXT: stwx r5, r4, r3764; CHECK-BE-NEXT: lwz r3, 1024(r1)765; CHECK-BE-NEXT: mr r1, r30766; CHECK-BE-NEXT: ld r30, -16(r1)767; CHECK-BE-NEXT: blr768;769; CHECK-32-LABEL: f10:770; CHECK-32: # %bb.0:771; CHECK-32-NEXT: clrlwi r12, r1, 22772; CHECK-32-NEXT: sub r0, r1, r12773; CHECK-32-NEXT: li r12, -5120774; CHECK-32-NEXT: add r0, r12, r0775; CHECK-32-NEXT: sub r12, r0, r1776; CHECK-32-NEXT: mr r0, r1777; CHECK-32-NEXT: cmpwi r12, -4096778; CHECK-32-NEXT: bge cr0, .LBB10_2779; CHECK-32-NEXT: .LBB10_1:780; CHECK-32-NEXT: stwu r0, -4096(r1)781; CHECK-32-NEXT: addi r12, r12, 4096782; CHECK-32-NEXT: cmpwi r12, -4096783; CHECK-32-NEXT: blt cr0, .LBB10_1784; CHECK-32-NEXT: .LBB10_2:785; CHECK-32-NEXT: stwux r0, r1, r12786; CHECK-32-NEXT: .cfi_def_cfa_register r0787; CHECK-32-NEXT: sub r0, r1, r0788; CHECK-32-NEXT: sub r0, r1, r0789; CHECK-32-NEXT: addic r0, r0, -8790; CHECK-32-NEXT: stwx r30, 0, r0791; CHECK-32-NEXT: addic r30, r0, 8792; CHECK-32-NEXT: .cfi_def_cfa_register r30793; CHECK-32-NEXT: .cfi_offset r30, -8794; CHECK-32-NEXT: addi r3, r1, 1024795; CHECK-32-NEXT: li r5, 1796; CHECK-32-NEXT: slwi r4, r4, 2797; CHECK-32-NEXT: stwx r5, r3, r4798; CHECK-32-NEXT: mr r0, r31799; CHECK-32-NEXT: lwz r3, 1024(r1)800; CHECK-32-NEXT: lwz r31, 0(r1)801; CHECK-32-NEXT: lwz r30, -8(r31)802; CHECK-32-NEXT: mr r1, r31803; CHECK-32-NEXT: mr r31, r0804; CHECK-32-NEXT: blr805 %a = alloca i32, i32 1000, align 1024806 %b = getelementptr inbounds i32, ptr %a, i64 %i807 store volatile i32 1, ptr %b808 %c = load volatile i32, ptr %a809 ret i32 %c810}811 812define void @f11(i32 %vla_size, i64 %i) #0 {813; CHECK-LE-LABEL: f11:814; CHECK-LE: # %bb.0:815; CHECK-LE-NEXT: clrldi r12, r1, 49816; CHECK-LE-NEXT: std r31, -8(r1)817; CHECK-LE-NEXT: std r30, -16(r1)818; CHECK-LE-NEXT: mr r30, r1819; CHECK-LE-NEXT: sub r0, r1, r12820; CHECK-LE-NEXT: lis r12, -2821; CHECK-LE-NEXT: ori r12, r12, 32768822; CHECK-LE-NEXT: add r0, r12, r0823; CHECK-LE-NEXT: sub r12, r0, r1824; CHECK-LE-NEXT: cmpdi r12, -4096825; CHECK-LE-NEXT: bge cr0, .LBB11_2826; CHECK-LE-NEXT: .LBB11_1:827; CHECK-LE-NEXT: stdu r30, -4096(r1)828; CHECK-LE-NEXT: addi r12, r12, 4096829; CHECK-LE-NEXT: cmpdi r12, -4096830; CHECK-LE-NEXT: blt cr0, .LBB11_1831; CHECK-LE-NEXT: .LBB11_2:832; CHECK-LE-NEXT: stdux r30, r1, r12833; CHECK-LE-NEXT: mr r0, r30834; CHECK-LE-NEXT: .cfi_def_cfa_register r0835; CHECK-LE-NEXT: .cfi_def_cfa_register r30836; CHECK-LE-NEXT: .cfi_offset r31, -8837; CHECK-LE-NEXT: .cfi_offset r30, -16838; CHECK-LE-NEXT: clrldi r3, r3, 32839; CHECK-LE-NEXT: lis r5, 1840; CHECK-LE-NEXT: mr r31, r1841; CHECK-LE-NEXT: li r6, 1842; CHECK-LE-NEXT: sldi r4, r4, 2843; CHECK-LE-NEXT: addi r3, r3, 15844; CHECK-LE-NEXT: ori r5, r5, 0845; CHECK-LE-NEXT: rldicl r3, r3, 60, 4846; CHECK-LE-NEXT: add r5, r31, r5847; CHECK-LE-NEXT: rldicl r3, r3, 4, 31848; CHECK-LE-NEXT: stwx r6, r5, r4849; CHECK-LE-NEXT: li r4, -32768850; CHECK-LE-NEXT: li r6, -4096851; CHECK-LE-NEXT: neg r5, r3852; CHECK-LE-NEXT: ld r3, 0(r1)853; CHECK-LE-NEXT: and r4, r5, r4854; CHECK-LE-NEXT: mr r5, r4855; CHECK-LE-NEXT: divd r7, r5, r6856; CHECK-LE-NEXT: add r4, r1, r5857; CHECK-LE-NEXT: mulld r6, r7, r6858; CHECK-LE-NEXT: sub r5, r5, r6859; CHECK-LE-NEXT: stdux r3, r1, r5860; CHECK-LE-NEXT: cmpd r1, r4861; CHECK-LE-NEXT: beq cr0, .LBB11_4862; CHECK-LE-NEXT: .LBB11_3:863; CHECK-LE-NEXT: stdu r3, -4096(r1)864; CHECK-LE-NEXT: cmpd r1, r4865; CHECK-LE-NEXT: bne cr0, .LBB11_3866; CHECK-LE-NEXT: .LBB11_4:867; CHECK-LE-NEXT: addi r3, r1, -32768868; CHECK-LE-NEXT: lbz r3, 0(r3)869; CHECK-LE-NEXT: mr r1, r30870; CHECK-LE-NEXT: ld r31, -8(r1)871; CHECK-LE-NEXT: ld r30, -16(r1)872; CHECK-LE-NEXT: blr873;874; CHECK-BE-LABEL: f11:875; CHECK-BE: # %bb.0:876; CHECK-BE-NEXT: clrldi r12, r1, 49877; CHECK-BE-NEXT: std r31, -8(r1)878; CHECK-BE-NEXT: std r30, -16(r1)879; CHECK-BE-NEXT: mr r30, r1880; CHECK-BE-NEXT: sub r0, r1, r12881; CHECK-BE-NEXT: lis r12, -2882; CHECK-BE-NEXT: ori r12, r12, 32768883; CHECK-BE-NEXT: add r0, r12, r0884; CHECK-BE-NEXT: sub r12, r0, r1885; CHECK-BE-NEXT: cmpdi r12, -4096886; CHECK-BE-NEXT: bge cr0, .LBB11_2887; CHECK-BE-NEXT: .LBB11_1:888; CHECK-BE-NEXT: stdu r30, -4096(r1)889; CHECK-BE-NEXT: addi r12, r12, 4096890; CHECK-BE-NEXT: cmpdi r12, -4096891; CHECK-BE-NEXT: blt cr0, .LBB11_1892; CHECK-BE-NEXT: .LBB11_2:893; CHECK-BE-NEXT: stdux r30, r1, r12894; CHECK-BE-NEXT: mr r0, r30895; CHECK-BE-NEXT: .cfi_def_cfa_register r0896; CHECK-BE-NEXT: .cfi_def_cfa_register r30897; CHECK-BE-NEXT: .cfi_offset r31, -8898; CHECK-BE-NEXT: .cfi_offset r30, -16899; CHECK-BE-NEXT: clrldi r3, r3, 32900; CHECK-BE-NEXT: lis r5, 1901; CHECK-BE-NEXT: addi r3, r3, 15902; CHECK-BE-NEXT: mr r31, r1903; CHECK-BE-NEXT: ori r5, r5, 0904; CHECK-BE-NEXT: rldicl r3, r3, 60, 4905; CHECK-BE-NEXT: add r5, r31, r5906; CHECK-BE-NEXT: sldi r4, r4, 2907; CHECK-BE-NEXT: li r6, 1908; CHECK-BE-NEXT: rldicl r3, r3, 4, 31909; CHECK-BE-NEXT: stwx r6, r5, r4910; CHECK-BE-NEXT: neg r7, r3911; CHECK-BE-NEXT: li r4, -32768912; CHECK-BE-NEXT: and r4, r7, r4913; CHECK-BE-NEXT: ld r3, 0(r1)914; CHECK-BE-NEXT: mr r7, r4915; CHECK-BE-NEXT: li r4, -4096916; CHECK-BE-NEXT: divd r5, r7, r4917; CHECK-BE-NEXT: mulld r4, r5, r4918; CHECK-BE-NEXT: sub r5, r7, r4919; CHECK-BE-NEXT: add r4, r1, r7920; CHECK-BE-NEXT: stdux r3, r1, r5921; CHECK-BE-NEXT: cmpd r1, r4922; CHECK-BE-NEXT: beq cr0, .LBB11_4923; CHECK-BE-NEXT: .LBB11_3:924; CHECK-BE-NEXT: stdu r3, -4096(r1)925; CHECK-BE-NEXT: cmpd r1, r4926; CHECK-BE-NEXT: bne cr0, .LBB11_3927; CHECK-BE-NEXT: .LBB11_4:928; CHECK-BE-NEXT: addi r3, r1, -32768929; CHECK-BE-NEXT: lbz r3, 0(r3)930; CHECK-BE-NEXT: mr r1, r30931; CHECK-BE-NEXT: ld r31, -8(r1)932; CHECK-BE-NEXT: ld r30, -16(r1)933; CHECK-BE-NEXT: blr934;935; CHECK-32-LABEL: f11:936; CHECK-32: # %bb.0:937; CHECK-32-NEXT: clrlwi r12, r1, 17938; CHECK-32-NEXT: sub r0, r1, r12939; CHECK-32-NEXT: lis r12, -2940; CHECK-32-NEXT: ori r12, r12, 32768941; CHECK-32-NEXT: add r0, r12, r0942; CHECK-32-NEXT: sub r12, r0, r1943; CHECK-32-NEXT: mr r0, r1944; CHECK-32-NEXT: cmpwi r12, -4096945; CHECK-32-NEXT: bge cr0, .LBB11_2946; CHECK-32-NEXT: .LBB11_1:947; CHECK-32-NEXT: stwu r0, -4096(r1)948; CHECK-32-NEXT: addi r12, r12, 4096949; CHECK-32-NEXT: cmpwi r12, -4096950; CHECK-32-NEXT: blt cr0, .LBB11_1951; CHECK-32-NEXT: .LBB11_2:952; CHECK-32-NEXT: stwux r0, r1, r12953; CHECK-32-NEXT: .cfi_def_cfa_register r0954; CHECK-32-NEXT: sub r0, r1, r0955; CHECK-32-NEXT: sub r0, r1, r0956; CHECK-32-NEXT: addic r0, r0, -4957; CHECK-32-NEXT: stwx r31, 0, r0958; CHECK-32-NEXT: addic r0, r0, -4959; CHECK-32-NEXT: stwx r30, 0, r0960; CHECK-32-NEXT: addic r30, r0, 8961; CHECK-32-NEXT: .cfi_def_cfa_register r30962; CHECK-32-NEXT: .cfi_offset r31, -4963; CHECK-32-NEXT: .cfi_offset r30, -8964; CHECK-32-NEXT: lis r4, 1965; CHECK-32-NEXT: mr r31, r1966; CHECK-32-NEXT: ori r4, r4, 0967; CHECK-32-NEXT: addi r3, r3, 15968; CHECK-32-NEXT: add r4, r31, r4969; CHECK-32-NEXT: li r5, 1970; CHECK-32-NEXT: slwi r6, r6, 2971; CHECK-32-NEXT: rlwinm r3, r3, 0, 0, 27972; CHECK-32-NEXT: neg r7, r3973; CHECK-32-NEXT: stwx r5, r4, r6974; CHECK-32-NEXT: li r4, -32768975; CHECK-32-NEXT: and r4, r7, r4976; CHECK-32-NEXT: lwz r3, 0(r1)977; CHECK-32-NEXT: mr r7, r4978; CHECK-32-NEXT: li r4, -4096979; CHECK-32-NEXT: divw r5, r7, r4980; CHECK-32-NEXT: mullw r4, r5, r4981; CHECK-32-NEXT: sub r5, r7, r4982; CHECK-32-NEXT: add r4, r1, r7983; CHECK-32-NEXT: stwux r3, r1, r5984; CHECK-32-NEXT: cmpw r1, r4985; CHECK-32-NEXT: beq cr0, .LBB11_4986; CHECK-32-NEXT: .LBB11_3:987; CHECK-32-NEXT: stwu r3, -4096(r1)988; CHECK-32-NEXT: cmpw r1, r4989; CHECK-32-NEXT: bne cr0, .LBB11_3990; CHECK-32-NEXT: .LBB11_4:991; CHECK-32-NEXT: addi r3, r1, -32768992; CHECK-32-NEXT: lbz r3, 0(r3)993; CHECK-32-NEXT: lwz r31, 0(r1)994; CHECK-32-NEXT: lwz r0, -4(r31)995; CHECK-32-NEXT: lwz r30, -8(r31)996; CHECK-32-NEXT: mr r1, r31997; CHECK-32-NEXT: mr r31, r0998; CHECK-32-NEXT: blr999 %a = alloca i32, i32 4096, align 327681000 %b = getelementptr inbounds i32, ptr %a, i64 %i1001 store volatile i32 1, ptr %b1002 %1 = zext i32 %vla_size to i641003 %vla = alloca i8, i64 %1, align 20481004 %2 = load volatile i8, ptr %vla, align 20481005 ret void1006}1007 1008attributes #0 = { "probe-stack"="inline-asm" }1009