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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=generic -verify-machineinstrs < %s | FileCheck %s3 4target datalayout = "E-m:a-p:32:32-i64:64-n32"5target triple = "powerpc-ibm-aix7.2.0.0"6 7%struct.USST = type { i16, i16 }8%struct.SST = type { i16, i16 }9%struct.CST = type { i8, i8 }10%struct.SCST = type { i8, i8 }11%struct.ST = type { i32, i32 }12%struct.UST = type { i32, i32 }13 14; Function Attrs: nounwind15define i32 @ustc1(ptr noundef byval(%struct.USST) align 4 %s) {16; CHECK-LABEL: ustc1:17; CHECK: # %bb.0: # %entry18; CHECK-NEXT: mr 4, 319; CHECK-NEXT: srwi 3, 3, 2420; CHECK-NEXT: stw 4, 24(1)21; CHECK-NEXT: blr22entry:23 %0 = load i16, ptr %s, align 424 %conv = zext i16 %0 to i3225 %shr = ashr i32 %conv, 826 ret i32 %shr27}28 29; Function Attrs: nounwind30define i32 @ustc2(ptr noundef byval(%struct.USST) align 4 %s) {31; CHECK-LABEL: ustc2:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: mr 4, 334; CHECK-NEXT: srwi 3, 3, 1635; CHECK-NEXT: stw 4, 24(1)36; CHECK-NEXT: blr37entry:38 %0 = load i16, ptr %s, align 439 %conv = zext i16 %0 to i3240 ret i32 %conv41}42 43; Function Attrs: nounwind44define i32 @stc1(ptr noundef byval(%struct.SST) align 4 %s) {45; CHECK-LABEL: stc1:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: mr 4, 348; CHECK-NEXT: srawi 3, 3, 2449; CHECK-NEXT: stw 4, 24(1)50; CHECK-NEXT: blr51entry:52 %0 = load i16, ptr %s, align 453 %conv = sext i16 %0 to i3254 %shr = ashr i32 %conv, 855 ret i32 %shr56}57 58; Function Attrs: nounwind59define i32 @stc2(ptr noundef byval(%struct.SST) align 4 %s) {60; CHECK-LABEL: stc2:61; CHECK: # %bb.0: # %entry62; CHECK-NEXT: mr 4, 363; CHECK-NEXT: srawi 3, 3, 1664; CHECK-NEXT: stw 4, 24(1)65; CHECK-NEXT: blr66entry:67 %0 = load i16, ptr %s, align 468 %conv = sext i16 %0 to i3269 ret i32 %conv70}71 72; Function Attrs: nounwind73define i32 @ctc(ptr noundef byval(%struct.CST) align 4 %s) {74; CHECK-LABEL: ctc:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: mr 4, 377; CHECK-NEXT: srwi 3, 3, 2478; CHECK-NEXT: stw 4, 24(1)79; CHECK-NEXT: blr80entry:81 %0 = load i8, ptr %s, align 482 %conv = zext i8 %0 to i3283 ret i32 %conv84}85 86; Function Attrs: nounwind87define i32 @sctc(ptr noundef byval(%struct.SCST) align 4 %s) {88; CHECK-LABEL: sctc:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: mr 4, 391; CHECK-NEXT: srawi 3, 3, 2492; CHECK-NEXT: stw 4, 24(1)93; CHECK-NEXT: blr94entry:95 %0 = load i8, ptr %s, align 496 %conv = sext i8 %0 to i3297 ret i32 %conv98}99 100; Function Attrs: nounwind101define i32 @tc44(ptr noundef byval(%struct.ST) align 4 %s) {102; CHECK-LABEL: tc44:103; CHECK: # %bb.0: # %entry104; CHECK-NEXT: stw 3, 24(1)105; CHECK-NEXT: stw 4, 28(1)106; CHECK-NEXT: blr107entry:108 %0 = load i32, ptr %s, align 4109 ret i32 %0110}111 112; Function Attrs: nounwind113define i32 @tc41(ptr noundef byval(%struct.ST) align 4 %s) {114; CHECK-LABEL: tc41:115; CHECK: # %bb.0: # %entry116; CHECK-NEXT: stw 3, 24(1)117; CHECK-NEXT: srawi 3, 3, 24118; CHECK-NEXT: stw 4, 28(1)119; CHECK-NEXT: blr120entry:121 %0 = load i32, ptr %s, align 4122 %shr = ashr i32 %0, 24123 ret i32 %shr124}125 126; Function Attrs: nounwind127define i32 @tc42(ptr noundef byval(%struct.ST) align 4 %s) {128; CHECK-LABEL: tc42:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: stw 3, 24(1)131; CHECK-NEXT: srawi 3, 3, 16132; CHECK-NEXT: stw 4, 28(1)133; CHECK-NEXT: blr134entry:135 %0 = load i32, ptr %s, align 4136 %shr = ashr i32 %0, 16137 ret i32 %shr138}139 140; Function Attrs: nounwind141define i32 @tc43(ptr noundef byval(%struct.ST) align 4 %s) {142; CHECK-LABEL: tc43:143; CHECK: # %bb.0: # %entry144; CHECK-NEXT: stw 3, 24(1)145; CHECK-NEXT: srawi 3, 3, 8146; CHECK-NEXT: stw 4, 28(1)147; CHECK-NEXT: blr148entry:149 %0 = load i32, ptr %s, align 4150 %shr = ashr i32 %0, 8151 ret i32 %shr152}153 154; Function Attrs: nounwind155define i32 @utc44(ptr noundef byval(%struct.UST) align 4 %s) {156; CHECK-LABEL: utc44:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: stw 3, 24(1)159; CHECK-NEXT: stw 4, 28(1)160; CHECK-NEXT: blr161entry:162 %0 = load i32, ptr %s, align 4163 ret i32 %0164}165 166; Function Attrs: nounwind167define i32 @utc41(ptr noundef byval(%struct.UST) align 4 %s) {168; CHECK-LABEL: utc41:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: stw 3, 24(1)171; CHECK-NEXT: srwi 3, 3, 24172; CHECK-NEXT: stw 4, 28(1)173; CHECK-NEXT: blr174entry:175 %0 = load i32, ptr %s, align 4176 %shr = lshr i32 %0, 24177 ret i32 %shr178}179 180; Function Attrs: nounwind181define i32 @utc42(ptr noundef byval(%struct.UST) align 4 %s) {182; CHECK-LABEL: utc42:183; CHECK: # %bb.0: # %entry184; CHECK-NEXT: stw 3, 24(1)185; CHECK-NEXT: srwi 3, 3, 16186; CHECK-NEXT: stw 4, 28(1)187; CHECK-NEXT: blr188entry:189 %0 = load i32, ptr %s, align 4190 %shr = lshr i32 %0, 16191 ret i32 %shr192}193 194; Function Attrs: nounwind195define i32 @utc43(ptr noundef byval(%struct.UST) align 4 %s) {196; CHECK-LABEL: utc43:197; CHECK: # %bb.0: # %entry198; CHECK-NEXT: stw 3, 24(1)199; CHECK-NEXT: srwi 3, 3, 8200; CHECK-NEXT: stw 4, 28(1)201; CHECK-NEXT: blr202entry:203 %0 = load i32, ptr %s, align 4204 %shr = lshr i32 %0, 8205 ret i32 %shr206}207