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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \4; RUN: < %s | FileCheck %s --check-prefix=CHECK-LE5 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \7; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \8; RUN: < %s | FileCheck %s --check-prefix=CHECK-BE9 10define void @test1(<4 x i32> %A, ptr %a) {11; CHECK-LE-LABEL: test1:12; CHECK-LE: # %bb.0: # %entry13; CHECK-LE-NEXT: stxvrwx v2, 0, r514; CHECK-LE-NEXT: blr15;16; CHECK-BE-LABEL: test1:17; CHECK-BE: # %bb.0: # %entry18; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 319; CHECK-BE-NEXT: stfiwx f0, 0, r520; CHECK-BE-NEXT: blr21entry:22 %vecext = extractelement <4 x i32> %A, i32 023 store i32 %vecext, ptr %a, align 424 ret void25}26 27define void @test2(<4 x float> %A, ptr %a) {28; CHECK-LE-LABEL: test2:29; CHECK-LE: # %bb.0: # %entry30; CHECK-LE-NEXT: stxvrwx v2, 0, r531; CHECK-LE-NEXT: blr32;33; CHECK-BE-LABEL: test2:34; CHECK-BE: # %bb.0: # %entry35; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 336; CHECK-BE-NEXT: stfiwx f0, 0, r537; CHECK-BE-NEXT: blr38entry:39 %vecext = extractelement <4 x float> %A, i32 040 store float %vecext, ptr %a, align 441 ret void42}43 44define void @test3(<2 x double> %A, ptr %a) {45; CHECK-LE-LABEL: test3:46; CHECK-LE: # %bb.0: # %entry47; CHECK-LE-NEXT: stxvrdx v2, 0, r548; CHECK-LE-NEXT: blr49;50; CHECK-BE-LABEL: test3:51; CHECK-BE: # %bb.0: # %entry52; CHECK-BE-NEXT: stxsd v2, 0(r5)53; CHECK-BE-NEXT: blr54entry:55 %vecext = extractelement <2 x double> %A, i32 056 store double %vecext, ptr %a, align 857 ret void58}59 60define void @test4(<2 x i64> %A, ptr %a) {61; CHECK-LE-LABEL: test4:62; CHECK-LE: # %bb.0: # %entry63; CHECK-LE-NEXT: stxvrdx v2, 0, r564; CHECK-LE-NEXT: blr65;66; CHECK-BE-LABEL: test4:67; CHECK-BE: # %bb.0: # %entry68; CHECK-BE-NEXT: stxsd v2, 0(r5)69; CHECK-BE-NEXT: blr70entry:71 %vecext = extractelement <2 x i64> %A, i32 072 store i64 %vecext, ptr %a, align 873 ret void74}75 76define void @test5(<8 x i16> %A, ptr %a) {77; CHECK-LE-LABEL: test5:78; CHECK-LE: # %bb.0: # %entry79; CHECK-LE-NEXT: stxvrhx v2, 0, r580; CHECK-LE-NEXT: blr81;82; CHECK-BE-LABEL: test5:83; CHECK-BE: # %bb.0: # %entry84; CHECK-BE-NEXT: vsldoi v2, v2, v2, 1085; CHECK-BE-NEXT: stxsihx v2, 0, r586; CHECK-BE-NEXT: blr87entry:88 %vecext = extractelement <8 x i16> %A, i32 089 store i16 %vecext, ptr %a, align 290 ret void91}92 93define void @test6(<16 x i8> %A, ptr %a) {94; CHECK-LE-LABEL: test6:95; CHECK-LE: # %bb.0: # %entry96; CHECK-LE-NEXT: stxvrbx v2, 0, r597; CHECK-LE-NEXT: blr98;99; CHECK-BE-LABEL: test6:100; CHECK-BE: # %bb.0: # %entry101; CHECK-BE-NEXT: vsldoi v2, v2, v2, 9102; CHECK-BE-NEXT: stxsibx v2, 0, r5103; CHECK-BE-NEXT: blr104entry:105 %vecext = extractelement <16 x i8> %A, i32 0106 store i8 %vecext, ptr %a, align 1107 ret void108}109 110