34 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s \3# RUN: -verify-coalescing --run-pass=register-coalescer -o - | FileCheck %s4 5# Check that the register coalescer correctly handles merging live ranges over6# SUBREG_TO_REG on PowerPC. The -verify-coalescing option will give an error if7# this is incorrect.8 9---10name: check_subregs11alignment: 1612tracksRegLiveness: true13body: |14 bb.0:15 liveins: $x316 17 ; CHECK-LABEL: name: check_subregs18 ; CHECK: liveins: $x319 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x321 ; CHECK-NEXT: [[LFSUX:%[0-9]+]]:f8rc, dead [[LFSUX1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LFSUX [[COPY]], [[COPY]]22 ; CHECK-NEXT: undef [[FRSP:%[0-9]+]].sub_64:vslrc = FRSP [[LFSUX]], implicit $rm23 ; CHECK-NEXT: [[XVCVDPSP:%[0-9]+]]:vrrc = XVCVDPSP [[FRSP]], implicit $rm24 ; CHECK-NEXT: $v2 = COPY [[XVCVDPSP]]25 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $v226 %0:g8rc_and_g8rc_nox0 = COPY $x327 %1:f8rc, %2:g8rc_and_g8rc_nox0 = LFSUX %0, %028 %3:f4rc = FRSP killed %1, implicit $rm29 %4:vslrc = SUBREG_TO_REG 1, %3, %subreg.sub_6430 %5:vrrc = XVCVDPSP killed %4, implicit $rm31 $v2 = COPY %532 BLR8 implicit $lr8, implicit $rm, implicit $v233...34