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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le < %s | FileCheck %s3 4define i64 @test1(ptr %a, ptr %b) {5; CHECK-LABEL: test1:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: ld 5, 0(3)8; CHECK-NEXT: ld 6, 0(4)9; CHECK-NEXT: mtvsrd 34, 510; CHECK-NEXT: mtvsrd 35, 611; CHECK-NEXT: add 4, 5, 612; CHECK-NEXT: vavgsb 2, 2, 313; CHECK-NEXT: stxsdx 34, 0, 314; CHECK-NEXT: mr 3, 415; CHECK-NEXT: blr16entry:17 %lhs = load i64, ptr %a, align 818 %rhs = load i64, ptr %b, align 819 %sum = add i64 %lhs, %rhs20 %lv = insertelement <2 x i64> undef, i64 %lhs, i32 021 %rv = insertelement <2 x i64> undef, i64 %rhs, i32 022 %lhc = bitcast <2 x i64> %lv to <16 x i8>23 %rhc = bitcast <2 x i64> %rv to <16 x i8>24 %add = call <16 x i8> @llvm.ppc.altivec.vavgsb(<16 x i8> %lhc, <16 x i8> %rhc)25 %cb = bitcast <16 x i8> %add to <2 x i64>26 %fv = extractelement <2 x i64> %cb, i32 027 store i64 %fv, ptr %a, align 828 ret i64 %sum29}30 31define i64 @test2(ptr %a, ptr %b) {32; CHECK-LABEL: test2:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: ld 5, 0(3)35; CHECK-NEXT: ld 6, 0(4)36; CHECK-NEXT: mtvsrd 34, 537; CHECK-NEXT: mtvsrd 35, 638; CHECK-NEXT: add 4, 5, 639; CHECK-NEXT: vadduhm 2, 2, 340; CHECK-NEXT: stxsdx 34, 0, 341; CHECK-NEXT: mr 3, 442; CHECK-NEXT: blr43entry:44 %lhs = load i64, ptr %a, align 845 %rhs = load i64, ptr %b, align 846 %sum = add i64 %lhs, %rhs47 %lv = insertelement <2 x i64> undef, i64 %lhs, i32 048 %rv = insertelement <2 x i64> undef, i64 %rhs, i32 049 %lhc = bitcast <2 x i64> %lv to <8 x i16>50 %rhc = bitcast <2 x i64> %rv to <8 x i16>51 %add = add <8 x i16> %lhc, %rhc52 %cb = bitcast <8 x i16> %add to <2 x i64>53 %fv = extractelement <2 x i64> %cb, i32 054 store i64 %fv, ptr %a, align 855 ret i64 %sum56}57 58; Ensure that vec-ops with multiple uses aren't simplified.59define signext i16 @vecop_uses(ptr %addr) {60; CHECK-LABEL: vecop_uses:61; CHECK: # %bb.0: # %entry62; CHECK-NEXT: li 4, 1663; CHECK-NEXT: lxvd2x 0, 3, 464; CHECK-NEXT: xxswapd 34, 065; CHECK-NEXT: lxvd2x 0, 0, 366; CHECK-NEXT: xxswapd 35, 067; CHECK-NEXT: vminsh 2, 3, 268; CHECK-NEXT: xxswapd 35, 3469; CHECK-NEXT: vminsh 2, 2, 370; CHECK-NEXT: xxspltw 35, 34, 271; CHECK-NEXT: vminsh 2, 2, 372; CHECK-NEXT: vsplth 3, 2, 673; CHECK-NEXT: vminsh 2, 2, 374; CHECK-NEXT: xxswapd 0, 3475; CHECK-NEXT: mffprd 3, 076; CHECK-NEXT: clrldi 3, 3, 4877; CHECK-NEXT: extsh 3, 378; CHECK-NEXT: blr79entry:80 %0 = load <16 x i16>, ptr %addr, align 281 %1 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %0)82 ret i16 %183}84 85define signext i32 @vecop_uses2(ptr %a, ptr %b, ptr %c) {86; CHECK-LABEL: vecop_uses2:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: lxvd2x 0, 0, 389; CHECK-NEXT: xxswapd 34, 090; CHECK-NEXT: lxvd2x 0, 0, 491; CHECK-NEXT: xxswapd 35, 092; CHECK-NEXT: xxsldwi 0, 34, 34, 393; CHECK-NEXT: vmuluwm 2, 3, 294; CHECK-NEXT: mffprwz 3, 095; CHECK-NEXT: extsw 3, 396; CHECK-NEXT: xxswapd 1, 3497; CHECK-NEXT: stxvd2x 1, 0, 598; CHECK-NEXT: blr99entry:100 %0 = load <4 x i32>, ptr %a, align 4101 %1 = load <4 x i32>, ptr %b, align 4102 %2 = mul <4 x i32> %1, %0103 store <4 x i32> %2, ptr %c, align 4104 %3 = extractelement <4 x i32> %0, i32 3105 ret i32 %3106}107 108declare <16 x i8> @llvm.ppc.altivec.vavgsb(<16 x i8>, <16 x i8>)109declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>)110