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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \3; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \4; RUN: -O3 < %s | FileCheck %s5 6; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \7; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \8; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \9; RUN: --implicit-check-not xxswapd10 11; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \12; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \13; RUN: -mattr=-power9-vector < %s | FileCheck %s --check-prefix=CHECK-P9-NOVECTOR14 15; These tests verify that VSX swap optimization works when loading a scalar16; into a vector register.17 18 19@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 1620@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 1621@y = global double 1.780000e+00, align 822 23define void @bar0() {24; CHECK-LABEL: bar0:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: addis r3, r2, .LC0@toc@ha27; CHECK-NEXT: ld r3, .LC0@toc@l(r3)28; CHECK-NEXT: lxvd2x vs0, 0, r329; CHECK-NEXT: addis r3, r2, .LC1@toc@ha30; CHECK-NEXT: ld r3, .LC1@toc@l(r3)31; CHECK-NEXT: lfd f1, 0(r3)32; CHECK-NEXT: addis r3, r2, .LC2@toc@ha33; CHECK-NEXT: ld r3, .LC2@toc@l(r3)34; CHECK-NEXT: xxswapd vs0, vs035; CHECK-NEXT: xxmrghd vs0, vs0, vs136; CHECK-NEXT: xxswapd vs0, vs037; CHECK-NEXT: stxvd2x vs0, 0, r338; CHECK-NEXT: blr39;40; CHECK-P9-LABEL: bar0:41; CHECK-P9: # %bb.0: # %entry42; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha43; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3)44; CHECK-P9-NEXT: lxv vs0, 0(r3)45; CHECK-P9-NEXT: addis r3, r2, .LC1@toc@ha46; CHECK-P9-NEXT: ld r3, .LC1@toc@l(r3)47; CHECK-P9-NEXT: lfd f1, 0(r3)48; CHECK-P9-NEXT: addis r3, r2, .LC2@toc@ha49; CHECK-P9-NEXT: ld r3, .LC2@toc@l(r3)50; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs151; CHECK-P9-NEXT: stxv vs0, 0(r3)52; CHECK-P9-NEXT: blr53;54; CHECK-P9-NOVECTOR-LABEL: bar0:55; CHECK-P9-NOVECTOR: # %bb.0: # %entry56; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC0@toc@ha57; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC0@toc@l(r3)58; CHECK-P9-NOVECTOR-NEXT: lxvd2x vs0, 0, r359; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC1@toc@ha60; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC1@toc@l(r3)61; CHECK-P9-NOVECTOR-NEXT: xxswapd vs0, vs062; CHECK-P9-NOVECTOR-NEXT: lfd f1, 0(r3)63; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC2@toc@ha64; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC2@toc@l(r3)65; CHECK-P9-NOVECTOR-NEXT: xxmrghd vs0, vs0, vs166; CHECK-P9-NOVECTOR-NEXT: xxswapd vs0, vs067; CHECK-P9-NOVECTOR-NEXT: stxvd2x vs0, 0, r368; CHECK-P9-NOVECTOR-NEXT: blr69entry:70 %0 = load <2 x double>, ptr @x, align 1671 %1 = load double, ptr @y, align 872 %vecins = insertelement <2 x double> %0, double %1, i32 073 store <2 x double> %vecins, ptr @z, align 1674 ret void75}76 77define void @bar1() {78; CHECK-LABEL: bar1:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: addis r3, r2, .LC0@toc@ha81; CHECK-NEXT: ld r3, .LC0@toc@l(r3)82; CHECK-NEXT: lxvd2x vs0, 0, r383; CHECK-NEXT: addis r3, r2, .LC1@toc@ha84; CHECK-NEXT: ld r3, .LC1@toc@l(r3)85; CHECK-NEXT: lfd f1, 0(r3)86; CHECK-NEXT: addis r3, r2, .LC2@toc@ha87; CHECK-NEXT: ld r3, .LC2@toc@l(r3)88; CHECK-NEXT: xxswapd vs0, vs089; CHECK-NEXT: xxpermdi vs0, vs1, vs0, 190; CHECK-NEXT: xxswapd vs0, vs091; CHECK-NEXT: stxvd2x vs0, 0, r392; CHECK-NEXT: blr93;94; CHECK-P9-LABEL: bar1:95; CHECK-P9: # %bb.0: # %entry96; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha97; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3)98; CHECK-P9-NEXT: lxv vs0, 0(r3)99; CHECK-P9-NEXT: addis r3, r2, .LC1@toc@ha100; CHECK-P9-NEXT: ld r3, .LC1@toc@l(r3)101; CHECK-P9-NEXT: lfd f1, 0(r3)102; CHECK-P9-NEXT: addis r3, r2, .LC2@toc@ha103; CHECK-P9-NEXT: ld r3, .LC2@toc@l(r3)104; CHECK-P9-NEXT: xxpermdi vs0, vs1, vs0, 1105; CHECK-P9-NEXT: stxv vs0, 0(r3)106; CHECK-P9-NEXT: blr107;108; CHECK-P9-NOVECTOR-LABEL: bar1:109; CHECK-P9-NOVECTOR: # %bb.0: # %entry110; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC0@toc@ha111; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC0@toc@l(r3)112; CHECK-P9-NOVECTOR-NEXT: lxvd2x vs0, 0, r3113; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC1@toc@ha114; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC1@toc@l(r3)115; CHECK-P9-NOVECTOR-NEXT: xxswapd vs0, vs0116; CHECK-P9-NOVECTOR-NEXT: lfd f1, 0(r3)117; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC2@toc@ha118; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC2@toc@l(r3)119; CHECK-P9-NOVECTOR-NEXT: xxpermdi vs0, vs1, vs0, 1120; CHECK-P9-NOVECTOR-NEXT: xxswapd vs0, vs0121; CHECK-P9-NOVECTOR-NEXT: stxvd2x vs0, 0, r3122; CHECK-P9-NOVECTOR-NEXT: blr123entry:124 %0 = load <2 x double>, ptr @x, align 16125 %1 = load double, ptr @y, align 8126 %vecins = insertelement <2 x double> %0, double %1, i32 1127 store <2 x double> %vecins, ptr @z, align 16128 ret void129}130 131