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1; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s2; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s3; RUN: llc -verify-machineinstrs -mtriple=ppc32-- -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0-32 %s4; RUN: llc -verify-machineinstrs -mtriple=ppc32-- -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1-32 %s5 6target triple = "powerpc64-unknown-linux-gnu"7; Test correct assembly code generation for thread-local storage using8; the local dynamic model.9 10@a = hidden thread_local global i32 0, align 411 12define signext i32 @main() nounwind {13entry:14 %retval = alloca i32, align 415 store i32 0, ptr %retval16 %0 = load i32, ptr @a, align 417 ret i32 %018}19 20; OPT0-LABEL: main:21; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha22; OPT0: addi 3, [[REG]], a@got@tlsld@l23; OPT0: bl __tls_get_addr(a@tlsld)24; OPT0-NEXT: nop25; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha26; OPT0: addi {{[0-9]+}}, [[REG2]], a@dtprel@l27; OPT0-32-LABEL: main28; OPT0-32: addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld29; OPT0-32: bl __tls_get_addr(a@tlsld)@PLT30; OPT0-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha31; OPT0-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l32; OPT1-32-LABEL: main33; OPT1-32: addi 3, {{[0-9]+}}, a@got@tlsld34; OPT1-32: bl __tls_get_addr(a@tlsld)@PLT35; OPT1-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha36; OPT1-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l37 38; Test peephole optimization for thread-local storage using the39; local dynamic model.40 41; OPT1-LABEL: main:42; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha43; OPT1: addi 3, [[REG]], a@got@tlsld@l44; OPT1: bl __tls_get_addr(a@tlsld)45; OPT1-NEXT: nop46; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha47; OPT1: lwa {{[0-9]+}}, a@dtprel@l([[REG2]])48 49; Test correct assembly code generation for thread-local storage using50; the general dynamic model.51 52@a2 = thread_local global i32 0, align 453 54define signext i32 @main2() nounwind {55entry:56 %retval = alloca i32, align 457 store i32 0, ptr %retval58 %0 = load i32, ptr @a2, align 459 ret i32 %060}61 62; OPT1-LABEL: main263; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha64; OPT1: addi 3, [[REG]], a2@got@tlsgd@l65; OPT1: bl __tls_get_addr(a2@tlsgd)66; OPT1-NEXT: nop67; OPT1-32-LABEL: main268; OPT1-32: addi 3, {{[0-9]+}}, a2@got@tlsgd69; OPT1-32: bl __tls_get_addr(a2@tlsgd)@PLT70