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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \4; RUN: -check-prefix=P9BE5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \7; RUN: -check-prefix=P9LE8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \9; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \10; RUN: -check-prefix=P8BE11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \12; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \13; RUN: -check-prefix=P8LE14define dso_local <2 x double> @test1(<8 x i16> %a) {15; P9BE-LABEL: test1:16; P9BE: # %bb.0: # %entry17; P9BE-NEXT: vextractuh v3, v2, 018; P9BE-NEXT: vextractuh v2, v2, 219; P9BE-NEXT: xscvuxddp f0, v320; P9BE-NEXT: xscvuxddp f1, v221; P9BE-NEXT: xxmrghd v2, vs0, vs122; P9BE-NEXT: blr23;24; P9LE-LABEL: test1:25; P9LE: # %bb.0: # %entry26; P9LE-NEXT: vextractuh v3, v2, 1427; P9LE-NEXT: vextractuh v2, v2, 1228; P9LE-NEXT: xscvuxddp f0, v329; P9LE-NEXT: xscvuxddp f1, v230; P9LE-NEXT: xxmrghd v2, vs1, vs031; P9LE-NEXT: blr32;33; P8BE-LABEL: test1:34; P8BE: # %bb.0: # %entry35; P8BE-NEXT: mfvsrd r3, v236; P8BE-NEXT: rldicl r4, r3, 16, 4837; P8BE-NEXT: rldicl r3, r3, 32, 4838; P8BE-NEXT: clrlwi r4, r4, 1639; P8BE-NEXT: clrlwi r3, r3, 1640; P8BE-NEXT: mtfprwz f0, r441; P8BE-NEXT: mtfprwz f1, r342; P8BE-NEXT: xscvuxddp f0, f043; P8BE-NEXT: xscvuxddp f1, f144; P8BE-NEXT: xxmrghd v2, vs0, vs145; P8BE-NEXT: blr46;47; P8LE-LABEL: test1:48; P8LE: # %bb.0: # %entry49; P8LE-NEXT: xxswapd vs0, v250; P8LE-NEXT: mffprd r3, f051; P8LE-NEXT: clrldi r4, r3, 4852; P8LE-NEXT: rldicl r3, r3, 48, 4853; P8LE-NEXT: clrlwi r4, r4, 1654; P8LE-NEXT: clrlwi r3, r3, 1655; P8LE-NEXT: mtfprwz f0, r456; P8LE-NEXT: mtfprwz f1, r357; P8LE-NEXT: xscvuxddp f0, f058; P8LE-NEXT: xscvuxddp f1, f159; P8LE-NEXT: xxmrghd v2, vs1, vs060; P8LE-NEXT: blr61entry:62 %vecext = extractelement <8 x i16> %a, i32 063 %conv = uitofp i16 %vecext to double64 %vecinit = insertelement <2 x double> undef, double %conv, i32 065 %vecext1 = extractelement <8 x i16> %a, i32 166 %conv2 = uitofp i16 %vecext1 to double67 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 168 ret <2 x double> %vecinit369}70 71define dso_local <2 x double> @test2(<4 x i32> %a, <4 x i32> %b) {72; P9BE-LABEL: test2:73; P9BE: # %bb.0: # %entry74; P9BE-NEXT: xxextractuw f0, v2, 075; P9BE-NEXT: xxextractuw f1, v3, 476; P9BE-NEXT: xscvuxddp f0, f077; P9BE-NEXT: xscvuxddp f1, f178; P9BE-NEXT: xxmrghd v2, vs0, vs179; P9BE-NEXT: blr80;81; P9LE-LABEL: test2:82; P9LE: # %bb.0: # %entry83; P9LE-NEXT: xxextractuw f0, v2, 1284; P9LE-NEXT: xxextractuw f1, v3, 885; P9LE-NEXT: xscvuxddp f0, f086; P9LE-NEXT: xscvuxddp f1, f187; P9LE-NEXT: xxmrghd v2, vs1, vs088; P9LE-NEXT: blr89;90; P8BE-LABEL: test2:91; P8BE: # %bb.0: # %entry92; P8BE-NEXT: xxsldwi vs0, v2, v2, 393; P8BE-NEXT: mffprwz r3, f094; P8BE-NEXT: mtfprwz f0, r395; P8BE-NEXT: mfvsrwz r3, v396; P8BE-NEXT: mtfprwz f1, r397; P8BE-NEXT: xscvuxddp f0, f098; P8BE-NEXT: xscvuxddp f1, f199; P8BE-NEXT: xxmrghd v2, vs0, vs1100; P8BE-NEXT: blr101;102; P8LE-LABEL: test2:103; P8LE: # %bb.0: # %entry104; P8LE-NEXT: xxswapd vs0, v2105; P8LE-NEXT: xxsldwi vs1, v3, v3, 1106; P8LE-NEXT: mffprwz r3, f0107; P8LE-NEXT: mtfprwz f0, r3108; P8LE-NEXT: mffprwz r3, f1109; P8LE-NEXT: mtfprwz f1, r3110; P8LE-NEXT: xscvuxddp f0, f0111; P8LE-NEXT: xscvuxddp f1, f1112; P8LE-NEXT: xxmrghd v2, vs1, vs0113; P8LE-NEXT: blr114entry:115 %vecext = extractelement <4 x i32> %a, i32 0116 %conv = uitofp i32 %vecext to double117 %vecinit = insertelement <2 x double> undef, double %conv, i32 0118 %vecext1 = extractelement <4 x i32> %b, i32 1119 %conv2 = uitofp i32 %vecext1 to double120 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1121 ret <2 x double> %vecinit3122}123