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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs -vec-extabi < %s | FileCheck %s4 5define <16 x i8> @test_l_v16i8(ptr %p) #0 {6; CHECK-LABEL: test_l_v16i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: li 4, 159; CHECK-NEXT: lvsl 3, 0, 310; CHECK-NEXT: lvx 2, 3, 411; CHECK-NEXT: lvx 4, 0, 312; CHECK-NEXT: vperm 2, 4, 2, 313; CHECK-NEXT: blr14entry:15 %r = load <16 x i8>, ptr %p, align 116 ret <16 x i8> %r17 18}19 20define <32 x i8> @test_l_v32i8(ptr %p) #0 {21; CHECK-LABEL: test_l_v32i8:22; CHECK: # %bb.0: # %entry23; CHECK-NEXT: li 4, 3124; CHECK-NEXT: lvsl 4, 0, 325; CHECK-NEXT: lvx 2, 3, 426; CHECK-NEXT: li 4, 1627; CHECK-NEXT: lvx 5, 3, 428; CHECK-NEXT: vperm 3, 5, 2, 429; CHECK-NEXT: lvx 2, 0, 330; CHECK-NEXT: vperm 2, 2, 5, 431; CHECK-NEXT: blr32entry:33 %r = load <32 x i8>, ptr %p, align 134 ret <32 x i8> %r35 36}37 38define <8 x i16> @test_l_v8i16(ptr %p) #0 {39; CHECK-LABEL: test_l_v8i16:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: li 4, 1542; CHECK-NEXT: lvsl 3, 0, 343; CHECK-NEXT: lvx 2, 3, 444; CHECK-NEXT: lvx 4, 0, 345; CHECK-NEXT: vperm 2, 4, 2, 346; CHECK-NEXT: blr47entry:48 %r = load <8 x i16>, ptr %p, align 249 ret <8 x i16> %r50 51}52 53define <16 x i16> @test_l_v16i16(ptr %p) #0 {54; CHECK-LABEL: test_l_v16i16:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: li 4, 3157; CHECK-NEXT: lvsl 4, 0, 358; CHECK-NEXT: lvx 2, 3, 459; CHECK-NEXT: li 4, 1660; CHECK-NEXT: lvx 5, 3, 461; CHECK-NEXT: vperm 3, 5, 2, 462; CHECK-NEXT: lvx 2, 0, 363; CHECK-NEXT: vperm 2, 2, 5, 464; CHECK-NEXT: blr65entry:66 %r = load <16 x i16>, ptr %p, align 267 ret <16 x i16> %r68 69}70 71define <4 x i32> @test_l_v4i32(ptr %p) #0 {72; CHECK-LABEL: test_l_v4i32:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: li 4, 1575; CHECK-NEXT: lvsl 3, 0, 376; CHECK-NEXT: lvx 2, 3, 477; CHECK-NEXT: lvx 4, 0, 378; CHECK-NEXT: vperm 2, 4, 2, 379; CHECK-NEXT: blr80entry:81 %r = load <4 x i32>, ptr %p, align 482 ret <4 x i32> %r83 84}85 86define <8 x i32> @test_l_v8i32(ptr %p) #0 {87; CHECK-LABEL: test_l_v8i32:88; CHECK: # %bb.0: # %entry89; CHECK-NEXT: li 4, 3190; CHECK-NEXT: lvsl 4, 0, 391; CHECK-NEXT: lvx 2, 3, 492; CHECK-NEXT: li 4, 1693; CHECK-NEXT: lvx 5, 3, 494; CHECK-NEXT: vperm 3, 5, 2, 495; CHECK-NEXT: lvx 2, 0, 396; CHECK-NEXT: vperm 2, 2, 5, 497; CHECK-NEXT: blr98entry:99 %r = load <8 x i32>, ptr %p, align 4100 ret <8 x i32> %r101 102}103 104define <2 x i64> @test_l_v2i64(ptr %p) #0 {105; CHECK-LABEL: test_l_v2i64:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: lxvd2x 34, 0, 3108; CHECK-NEXT: blr109entry:110 %r = load <2 x i64>, ptr %p, align 8111 ret <2 x i64> %r112 113}114 115define <4 x i64> @test_l_v4i64(ptr %p) #0 {116; CHECK-LABEL: test_l_v4i64:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: li 4, 16119; CHECK-NEXT: lxvd2x 34, 0, 3120; CHECK-NEXT: lxvd2x 35, 3, 4121; CHECK-NEXT: blr122entry:123 %r = load <4 x i64>, ptr %p, align 8124 ret <4 x i64> %r125 126}127 128define <4 x float> @test_l_v4float(ptr %p) #0 {129; CHECK-LABEL: test_l_v4float:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: li 4, 15132; CHECK-NEXT: lvsl 3, 0, 3133; CHECK-NEXT: lvx 2, 3, 4134; CHECK-NEXT: lvx 4, 0, 3135; CHECK-NEXT: vperm 2, 4, 2, 3136; CHECK-NEXT: blr137entry:138 %r = load <4 x float>, ptr %p, align 4139 ret <4 x float> %r140 141}142 143define <8 x float> @test_l_v8float(ptr %p) #0 {144; CHECK-LABEL: test_l_v8float:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: li 4, 31147; CHECK-NEXT: lvsl 4, 0, 3148; CHECK-NEXT: lvx 2, 3, 4149; CHECK-NEXT: li 4, 16150; CHECK-NEXT: lvx 5, 3, 4151; CHECK-NEXT: vperm 3, 5, 2, 4152; CHECK-NEXT: lvx 2, 0, 3153; CHECK-NEXT: vperm 2, 2, 5, 4154; CHECK-NEXT: blr155entry:156 %r = load <8 x float>, ptr %p, align 4157 ret <8 x float> %r158 159}160 161define <2 x double> @test_l_v2double(ptr %p) #0 {162; CHECK-LABEL: test_l_v2double:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: lxvd2x 34, 0, 3165; CHECK-NEXT: blr166entry:167 %r = load <2 x double>, ptr %p, align 8168 ret <2 x double> %r169 170}171 172define <4 x double> @test_l_v4double(ptr %p) #0 {173; CHECK-LABEL: test_l_v4double:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: li 4, 16176; CHECK-NEXT: lxvd2x 34, 0, 3177; CHECK-NEXT: lxvd2x 35, 3, 4178; CHECK-NEXT: blr179entry:180 %r = load <4 x double>, ptr %p, align 8181 ret <4 x double> %r182 183}184 185define <16 x i8> @test_l_p8v16i8(ptr %p) #2 {186; CHECK-LABEL: test_l_p8v16i8:187; CHECK: # %bb.0: # %entry188; CHECK-NEXT: lxvw4x 34, 0, 3189; CHECK-NEXT: blr190entry:191 %r = load <16 x i8>, ptr %p, align 1192 ret <16 x i8> %r193 194}195 196define <32 x i8> @test_l_p8v32i8(ptr %p) #2 {197; CHECK-LABEL: test_l_p8v32i8:198; CHECK: # %bb.0: # %entry199; CHECK-NEXT: li 4, 16200; CHECK-NEXT: lxvw4x 34, 0, 3201; CHECK-NEXT: lxvw4x 35, 3, 4202; CHECK-NEXT: blr203entry:204 %r = load <32 x i8>, ptr %p, align 1205 ret <32 x i8> %r206 207}208 209define <8 x i16> @test_l_p8v8i16(ptr %p) #2 {210; CHECK-LABEL: test_l_p8v8i16:211; CHECK: # %bb.0: # %entry212; CHECK-NEXT: lxvw4x 34, 0, 3213; CHECK-NEXT: blr214entry:215 %r = load <8 x i16>, ptr %p, align 2216 ret <8 x i16> %r217 218}219 220define <16 x i16> @test_l_p8v16i16(ptr %p) #2 {221; CHECK-LABEL: test_l_p8v16i16:222; CHECK: # %bb.0: # %entry223; CHECK-NEXT: li 4, 16224; CHECK-NEXT: lxvw4x 34, 0, 3225; CHECK-NEXT: lxvw4x 35, 3, 4226; CHECK-NEXT: blr227entry:228 %r = load <16 x i16>, ptr %p, align 2229 ret <16 x i16> %r230 231}232 233define <4 x i32> @test_l_p8v4i32(ptr %p) #2 {234; CHECK-LABEL: test_l_p8v4i32:235; CHECK: # %bb.0: # %entry236; CHECK-NEXT: lxvw4x 34, 0, 3237; CHECK-NEXT: blr238entry:239 %r = load <4 x i32>, ptr %p, align 4240 ret <4 x i32> %r241 242}243 244define <8 x i32> @test_l_p8v8i32(ptr %p) #2 {245; CHECK-LABEL: test_l_p8v8i32:246; CHECK: # %bb.0: # %entry247; CHECK-NEXT: li 4, 16248; CHECK-NEXT: lxvw4x 34, 0, 3249; CHECK-NEXT: lxvw4x 35, 3, 4250; CHECK-NEXT: blr251entry:252 %r = load <8 x i32>, ptr %p, align 4253 ret <8 x i32> %r254 255}256 257define <2 x i64> @test_l_p8v2i64(ptr %p) #2 {258; CHECK-LABEL: test_l_p8v2i64:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: lxvd2x 34, 0, 3261; CHECK-NEXT: blr262entry:263 %r = load <2 x i64>, ptr %p, align 8264 ret <2 x i64> %r265 266}267 268define <4 x i64> @test_l_p8v4i64(ptr %p) #2 {269; CHECK-LABEL: test_l_p8v4i64:270; CHECK: # %bb.0: # %entry271; CHECK-NEXT: li 4, 16272; CHECK-NEXT: lxvd2x 34, 0, 3273; CHECK-NEXT: lxvd2x 35, 3, 4274; CHECK-NEXT: blr275entry:276 %r = load <4 x i64>, ptr %p, align 8277 ret <4 x i64> %r278 279}280 281define <4 x float> @test_l_p8v4float(ptr %p) #2 {282; CHECK-LABEL: test_l_p8v4float:283; CHECK: # %bb.0: # %entry284; CHECK-NEXT: lxvw4x 34, 0, 3285; CHECK-NEXT: blr286entry:287 %r = load <4 x float>, ptr %p, align 4288 ret <4 x float> %r289 290}291 292define <8 x float> @test_l_p8v8float(ptr %p) #2 {293; CHECK-LABEL: test_l_p8v8float:294; CHECK: # %bb.0: # %entry295; CHECK-NEXT: li 4, 16296; CHECK-NEXT: lxvw4x 34, 0, 3297; CHECK-NEXT: lxvw4x 35, 3, 4298; CHECK-NEXT: blr299entry:300 %r = load <8 x float>, ptr %p, align 4301 ret <8 x float> %r302 303}304 305define <2 x double> @test_l_p8v2double(ptr %p) #2 {306; CHECK-LABEL: test_l_p8v2double:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: lxvd2x 34, 0, 3309; CHECK-NEXT: blr310entry:311 %r = load <2 x double>, ptr %p, align 8312 ret <2 x double> %r313 314}315 316define <4 x double> @test_l_p8v4double(ptr %p) #2 {317; CHECK-LABEL: test_l_p8v4double:318; CHECK: # %bb.0: # %entry319; CHECK-NEXT: li 4, 16320; CHECK-NEXT: lxvd2x 34, 0, 3321; CHECK-NEXT: lxvd2x 35, 3, 4322; CHECK-NEXT: blr323entry:324 %r = load <4 x double>, ptr %p, align 8325 ret <4 x double> %r326 327}328 329define void @test_s_v16i8(ptr %p, <16 x i8> %v) #0 {330; CHECK-LABEL: test_s_v16i8:331; CHECK: # %bb.0: # %entry332; CHECK-NEXT: stxvw4x 34, 0, 3333; CHECK-NEXT: blr334entry:335 store <16 x i8> %v, ptr %p, align 1336 ret void337 338}339 340define void @test_s_v32i8(ptr %p, <32 x i8> %v) #0 {341; CHECK-LABEL: test_s_v32i8:342; CHECK: # %bb.0: # %entry343; CHECK-NEXT: li 4, 16344; CHECK-NEXT: stxvw4x 34, 0, 3345; CHECK-NEXT: stxvw4x 35, 3, 4346; CHECK-NEXT: blr347entry:348 store <32 x i8> %v, ptr %p, align 1349 ret void350 351}352 353define void @test_s_v8i16(ptr %p, <8 x i16> %v) #0 {354; CHECK-LABEL: test_s_v8i16:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: stxvw4x 34, 0, 3357; CHECK-NEXT: blr358entry:359 store <8 x i16> %v, ptr %p, align 2360 ret void361 362}363 364define void @test_s_v16i16(ptr %p, <16 x i16> %v) #0 {365; CHECK-LABEL: test_s_v16i16:366; CHECK: # %bb.0: # %entry367; CHECK-NEXT: li 4, 16368; CHECK-NEXT: stxvw4x 34, 0, 3369; CHECK-NEXT: stxvw4x 35, 3, 4370; CHECK-NEXT: blr371entry:372 store <16 x i16> %v, ptr %p, align 2373 ret void374 375}376 377define void @test_s_v4i32(ptr %p, <4 x i32> %v) #0 {378; CHECK-LABEL: test_s_v4i32:379; CHECK: # %bb.0: # %entry380; CHECK-NEXT: stxvw4x 34, 0, 3381; CHECK-NEXT: blr382entry:383 store <4 x i32> %v, ptr %p, align 4384 ret void385 386}387 388define void @test_s_v8i32(ptr %p, <8 x i32> %v) #0 {389; CHECK-LABEL: test_s_v8i32:390; CHECK: # %bb.0: # %entry391; CHECK-NEXT: li 4, 16392; CHECK-NEXT: stxvw4x 34, 0, 3393; CHECK-NEXT: stxvw4x 35, 3, 4394; CHECK-NEXT: blr395entry:396 store <8 x i32> %v, ptr %p, align 4397 ret void398 399}400 401define void @test_s_v2i64(ptr %p, <2 x i64> %v) #0 {402; CHECK-LABEL: test_s_v2i64:403; CHECK: # %bb.0: # %entry404; CHECK-NEXT: stxvd2x 34, 0, 3405; CHECK-NEXT: blr406entry:407 store <2 x i64> %v, ptr %p, align 8408 ret void409 410}411 412define void @test_s_v4i64(ptr %p, <4 x i64> %v) #0 {413; CHECK-LABEL: test_s_v4i64:414; CHECK: # %bb.0: # %entry415; CHECK-NEXT: li 4, 16416; CHECK-NEXT: stxvd2x 34, 0, 3417; CHECK-NEXT: stxvd2x 35, 3, 4418; CHECK-NEXT: blr419entry:420 store <4 x i64> %v, ptr %p, align 8421 ret void422 423}424 425define void @test_s_v4float(ptr %p, <4 x float> %v) #0 {426; CHECK-LABEL: test_s_v4float:427; CHECK: # %bb.0: # %entry428; CHECK-NEXT: stxvw4x 34, 0, 3429; CHECK-NEXT: blr430entry:431 store <4 x float> %v, ptr %p, align 4432 ret void433 434}435 436define void @test_s_v8float(ptr %p, <8 x float> %v) #0 {437; CHECK-LABEL: test_s_v8float:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: li 4, 16440; CHECK-NEXT: stxvw4x 34, 0, 3441; CHECK-NEXT: stxvw4x 35, 3, 4442; CHECK-NEXT: blr443entry:444 store <8 x float> %v, ptr %p, align 4445 ret void446 447}448 449define void @test_s_v2double(ptr %p, <2 x double> %v) #0 {450; CHECK-LABEL: test_s_v2double:451; CHECK: # %bb.0: # %entry452; CHECK-NEXT: stxvd2x 34, 0, 3453; CHECK-NEXT: blr454entry:455 store <2 x double> %v, ptr %p, align 8456 ret void457 458}459 460define void @test_s_v4double(ptr %p, <4 x double> %v) #0 {461; CHECK-LABEL: test_s_v4double:462; CHECK: # %bb.0: # %entry463; CHECK-NEXT: li 4, 16464; CHECK-NEXT: stxvd2x 34, 0, 3465; CHECK-NEXT: stxvd2x 35, 3, 4466; CHECK-NEXT: blr467entry:468 store <4 x double> %v, ptr %p, align 8469 ret void470 471}472 473attributes #0 = { nounwind "target-cpu"="pwr7" }474attributes #2 = { nounwind "target-cpu"="pwr8" }475 476