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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=-vsx| FileCheck %s3; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s4target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"5target triple = "powerpc64-unknown-linux-gnu"6 7define void @copy_to_conceal(ptr %inp) #0 {8; CHECK-LABEL: copy_to_conceal:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: addi 4, 1, -1611; CHECK-NEXT: vxor 2, 2, 212; CHECK-NEXT: stvx 2, 0, 413; CHECK-NEXT: ld 4, -8(1)14; CHECK-NEXT: std 4, 8(3)15; CHECK-NEXT: ld 4, -16(1)16; CHECK-NEXT: std 4, 0(3)17; CHECK-NEXT: blr18;19; CHECK-VSX-LABEL: copy_to_conceal:20; CHECK-VSX: # %bb.0: # %entry21; CHECK-VSX-NEXT: xxlxor 0, 0, 022; CHECK-VSX-NEXT: stxvw4x 0, 0, 323; CHECK-VSX-NEXT: blr24entry:25 store <8 x i16> zeroinitializer, ptr %inp, align 226 br label %if.end21027 28if.end210: ; preds = %entry29 ret void30 31; This will generate two align-1 i64 stores. Make sure that they are32; indexed stores and not in r+i form (which require the offset to be33; a multiple of 4).34 35}36 37attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" }38