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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-convert-rr-to-ri=false -ppc-asm-full-reg-names < %s | FileCheck %s3 4; ISEL matches address mode xaddr.5define i8 @test_xaddr(ptr %p) {6; CHECK-LABEL: test_xaddr:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: li r4, 09; CHECK-NEXT: std r3, -8(r1)10; CHECK-NEXT: ori r4, r4, 4000011; CHECK-NEXT: lbzx r3, r3, r412; CHECK-NEXT: blr13entry:14 %p.addr = alloca ptr, align 815 store ptr %p, ptr %p.addr, align 816 %0 = load ptr, ptr %p.addr, align 817 %add.ptr = getelementptr inbounds i8, ptr %0, i64 4000018 %1 = load i8, ptr %add.ptr, align 119 ret i8 %120}21 22; ISEL matches address mode xaddrX4.23define i64 @test_xaddrX4(ptr %p) {24; CHECK-LABEL: test_xaddrX4:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: li r4, 327; CHECK-NEXT: std r3, -8(r1)28; CHECK-NEXT: ldx r3, r3, r429; CHECK-NEXT: blr30entry:31 %p.addr = alloca ptr, align 832 store ptr %p, ptr %p.addr, align 833 %0 = load ptr, ptr %p.addr, align 834 %add.ptr = getelementptr inbounds i8, ptr %0, i64 335 %1 = load i64, ptr %add.ptr, align 836 ret i64 %137}38 39; ISEL matches address mode xaddrX16.40define <2 x double> @test_xaddrX16(ptr %arr) {41; CHECK-LABEL: test_xaddrX16:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: li r4, 4044; CHECK-NEXT: lxvx vs34, r3, r445; CHECK-NEXT: blr46entry:47 %arrayidx1 = getelementptr inbounds double, ptr %arr, i64 548 %0 = load <2 x double>, ptr %arrayidx1, align 1649 ret <2 x double> %050}51 52; ISEL matches address mode xoaddr.53define void @test_xoaddr(ptr %arr, ptr %arrTo) {54; CHECK-LABEL: test_xoaddr:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: li r5, 857; CHECK-NEXT: lxvx vs0, r3, r558; CHECK-NEXT: li r3, 459; CHECK-NEXT: stxvx vs0, r4, r360; CHECK-NEXT: blr61entry:62 %arrayidx = getelementptr inbounds i32, ptr %arrTo, i64 163 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 264 %0 = load <4 x i32>, ptr %arrayidx1, align 865 store <4 x i32> %0, ptr %arrayidx, align 866 ret void67}68 69; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of70; loop.71define i64 @test_xaddrX4_loop(ptr %p) {72; CHECK-LABEL: test_xaddrX4_loop:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: addi r4, r3, -875; CHECK-NEXT: li r3, 876; CHECK-NEXT: li r5, 377; CHECK-NEXT: mtctr r378; CHECK-NEXT: li r3, 079; CHECK-NEXT: .p2align 480; CHECK-NEXT: .LBB4_1: # %for.body81; CHECK-NEXT: #82; CHECK-NEXT: ldu r6, 8(r4)83; CHECK-NEXT: ldx r7, r4, r584; CHECK-NEXT: maddld r3, r7, r6, r385; CHECK-NEXT: bdnz .LBB4_186; CHECK-NEXT: # %bb.2: # %for.end87; CHECK-NEXT: blr88; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4.89entry:90 br label %for.body91 92for.body: ; preds = %for.body, %entry93 %i.015 = phi i64 [ 0, %entry ], [ %inc, %for.body ]94 %res.014 = phi i64 [ 0, %entry ], [ %add, %for.body ]95 %mul = shl i64 %i.015, 396 %add.ptr = getelementptr inbounds i8, ptr %p, i64 %mul97 %0 = load i64, ptr %add.ptr, align 898 %add.ptr3 = getelementptr inbounds i8, ptr %add.ptr, i64 399 %1 = load i64, ptr %add.ptr3, align 8100 %mul4 = mul i64 %1, %0101 %add = add i64 %mul4, %res.014102 %inc = add nuw nsw i64 %i.015, 1103 %exitcond = icmp eq i64 %inc, 8104 br i1 %exitcond, label %for.end, label %for.body105 106for.end: ; preds = %for.body107 ret i64 %add108 109}110