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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s3; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s4target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"5 6define void @foo1(ptr %p, ptr %r) nounwind {7; CHECK-LABEL: foo1:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: lhz 3, 0(3)10; CHECK-NEXT: sth 3, 0(4)11; CHECK-NEXT: blr12;13; CHECK-VSX-LABEL: foo1:14; CHECK-VSX: # %bb.0: # %entry15; CHECK-VSX-NEXT: lhz 3, 0(3)16; CHECK-VSX-NEXT: sth 3, 0(4)17; CHECK-VSX-NEXT: blr18entry:19 %v = load i16, ptr %p, align 120 store i16 %v, ptr %r, align 121 ret void22 23 24}25 26define void @foo2(ptr %p, ptr %r) nounwind {27; CHECK-LABEL: foo2:28; CHECK: # %bb.0: # %entry29; CHECK-NEXT: lwz 3, 0(3)30; CHECK-NEXT: stw 3, 0(4)31; CHECK-NEXT: blr32;33; CHECK-VSX-LABEL: foo2:34; CHECK-VSX: # %bb.0: # %entry35; CHECK-VSX-NEXT: lwz 3, 0(3)36; CHECK-VSX-NEXT: stw 3, 0(4)37; CHECK-VSX-NEXT: blr38entry:39 %v = load i32, ptr %p, align 140 store i32 %v, ptr %r, align 141 ret void42 43 44}45 46define void @foo3(ptr %p, ptr %r) nounwind {47; CHECK-LABEL: foo3:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: ld 3, 0(3)50; CHECK-NEXT: std 3, 0(4)51; CHECK-NEXT: blr52;53; CHECK-VSX-LABEL: foo3:54; CHECK-VSX: # %bb.0: # %entry55; CHECK-VSX-NEXT: ld 3, 0(3)56; CHECK-VSX-NEXT: std 3, 0(4)57; CHECK-VSX-NEXT: blr58entry:59 %v = load i64, ptr %p, align 160 store i64 %v, ptr %r, align 161 ret void62 63 64}65 66define void @foo4(ptr %p, ptr %r) nounwind {67; CHECK-LABEL: foo4:68; CHECK: # %bb.0: # %entry69; CHECK-NEXT: lwz 3, 0(3)70; CHECK-NEXT: stw 3, 0(4)71; CHECK-NEXT: blr72;73; CHECK-VSX-LABEL: foo4:74; CHECK-VSX: # %bb.0: # %entry75; CHECK-VSX-NEXT: lwz 3, 0(3)76; CHECK-VSX-NEXT: stw 3, 0(4)77; CHECK-VSX-NEXT: blr78entry:79 %v = load float, ptr %p, align 180 store float %v, ptr %r, align 181 ret void82 83 84}85 86define void @foo5(ptr %p, ptr %r) nounwind {87; CHECK-LABEL: foo5:88; CHECK: # %bb.0: # %entry89; CHECK-NEXT: ld 3, 0(3)90; CHECK-NEXT: std 3, 0(4)91; CHECK-NEXT: blr92;93; CHECK-VSX-LABEL: foo5:94; CHECK-VSX: # %bb.0: # %entry95; CHECK-VSX-NEXT: ld 3, 0(3)96; CHECK-VSX-NEXT: std 3, 0(4)97; CHECK-VSX-NEXT: blr98entry:99 %v = load double, ptr %p, align 1100 store double %v, ptr %r, align 1101 ret void102 103 104}105 106define void @foo6(ptr %p, ptr %r) nounwind {107; These loads and stores are legalized into aligned loads and stores108; using aligned stack slots.109; CHECK-LABEL: foo6:110; CHECK: # %bb.0: # %entry111; CHECK-NEXT: li 5, 15112; CHECK-NEXT: lvsl 3, 0, 3113; CHECK-NEXT: lvx 2, 3, 5114; CHECK-NEXT: lvx 4, 0, 3115; CHECK-NEXT: addi 3, 1, -16116; CHECK-NEXT: vperm 2, 4, 2, 3117; CHECK-NEXT: stvx 2, 0, 3118; CHECK-NEXT: ld 3, -8(1)119; CHECK-NEXT: std 3, 8(4)120; CHECK-NEXT: ld 3, -16(1)121; CHECK-NEXT: std 3, 0(4)122; CHECK-NEXT: blr123;124; CHECK-VSX-LABEL: foo6:125; CHECK-VSX: # %bb.0: # %entry126; CHECK-VSX-NEXT: li 5, 15127; CHECK-VSX-NEXT: lvsl 3, 0, 3128; CHECK-VSX-NEXT: lvx 2, 3, 5129; CHECK-VSX-NEXT: lvx 4, 0, 3130; CHECK-VSX-NEXT: vperm 2, 4, 2, 3131; CHECK-VSX-NEXT: stxvw4x 34, 0, 4132; CHECK-VSX-NEXT: blr133; For VSX on P7, unaligned loads and stores are preferable to aligned134; stack slots, but lvsl/vperm is better still. (On P8 lxvw4x is preferable.)135; Using unaligned stxvw4x is preferable on both machines.136entry:137 %v = load <4 x float>, ptr %p, align 1138 store <4 x float> %v, ptr %r, align 1139 ret void140}141 142