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1; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 <%s | FileCheck %s2 3; Test optimizations of build_vector for 6-bit immediates.4 5target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"6target triple = "powerpc64-unknown-linux-gnu"7 8%v4i32 = type <4 x i32>9%v8i16 = type <8 x i16>10%v16i8 = type <16 x i8>11 12define void @test_v4i32_pos_even(ptr %P, ptr %S) {13 %p = load %v4i32, ptr %P14 %r = add %v4i32 %p, < i32 18, i32 18, i32 18, i32 18 >15 store %v4i32 %r, ptr %S16 ret void17}18 19; CHECK-LABEL: test_v4i32_pos_even:20; CHECK: vspltisw [[REG1:[0-9]+]], 921; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]22 23define void @test_v4i32_neg_even(ptr %P, ptr %S) {24 %p = load %v4i32, ptr %P25 %r = add %v4i32 %p, < i32 -28, i32 -28, i32 -28, i32 -28 >26 store %v4i32 %r, ptr %S27 ret void28}29 30; CHECK-LABEL: test_v4i32_neg_even:31; CHECK: vspltisw [[REG1:[0-9]+]], -1432; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]33 34define void @test_v8i16_pos_even(ptr %P, ptr %S) {35 %p = load %v8i16, ptr %P36 %r = add %v8i16 %p, < i16 30, i16 30, i16 30, i16 30, i16 30, i16 30, i16 30, i16 30 >37 store %v8i16 %r, ptr %S38 ret void39}40 41; CHECK-LABEL: test_v8i16_pos_even:42; CHECK: vspltish [[REG1:[0-9]+]], 1543; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]44 45define void @test_v8i16_neg_even(ptr %P, ptr %S) {46 %p = load %v8i16, ptr %P47 %r = add %v8i16 %p, < i16 -32, i16 -32, i16 -32, i16 -32, i16 -32, i16 -32, i16 -32, i16 -32 >48 store %v8i16 %r, ptr %S49 ret void50}51 52; CHECK-LABEL: test_v8i16_neg_even:53; CHECK: vspltish [[REG1:[0-9]+]], -1654; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]55 56define void @test_v16i8_pos_even(ptr %P, ptr %S) {57 %p = load %v16i8, ptr %P58 %r = add %v16i8 %p, < i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16 >59 store %v16i8 %r, ptr %S60 ret void61}62 63; CHECK-LABEL: test_v16i8_pos_even:64; CHECK: vspltisb [[REG1:[0-9]+]], 865; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]66 67define void @test_v16i8_neg_even(ptr %P, ptr %S) {68 %p = load %v16i8, ptr %P69 %r = add %v16i8 %p, < i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18 >70 store %v16i8 %r, ptr %S71 ret void72}73 74; CHECK-LABEL: test_v16i8_neg_even:75; CHECK: vspltisb [[REG1:[0-9]+]], -976; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]77 78define void @test_v4i32_pos_odd(ptr %P, ptr %S) {79 %p = load %v4i32, ptr %P80 %r = add %v4i32 %p, < i32 27, i32 27, i32 27, i32 27 >81 store %v4i32 %r, ptr %S82 ret void83}84 85; CHECK-LABEL: test_v4i32_pos_odd:86; CHECK: vspltisw [[REG2:[0-9]+]], -1687; CHECK: vspltisw [[REG1:[0-9]+]], 1188; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]]89 90define void @test_v4i32_neg_odd(ptr %P, ptr %S) {91 %p = load %v4i32, ptr %P92 %r = add %v4i32 %p, < i32 -27, i32 -27, i32 -27, i32 -27 >93 store %v4i32 %r, ptr %S94 ret void95}96 97; CHECK-LABEL: test_v4i32_neg_odd:98; CHECK: vspltisw [[REG2:[0-9]+]], -1699; CHECK: vspltisw [[REG1:[0-9]+]], -11100; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]]101 102define void @test_v8i16_pos_odd(ptr %P, ptr %S) {103 %p = load %v8i16, ptr %P104 %r = add %v8i16 %p, < i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31 >105 store %v8i16 %r, ptr %S106 ret void107}108 109; CHECK-LABEL: test_v8i16_pos_odd:110; CHECK: vspltish [[REG2:[0-9]+]], -16111; CHECK: vspltish [[REG1:[0-9]+]], 15112; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]]113 114define void @test_v8i16_neg_odd(ptr %P, ptr %S) {115 %p = load %v8i16, ptr %P116 %r = add %v8i16 %p, < i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31 >117 store %v8i16 %r, ptr %S118 ret void119}120 121; CHECK-LABEL: test_v8i16_neg_odd:122; CHECK: vspltish [[REG2:[0-9]+]], -16123; CHECK: vspltish [[REG1:[0-9]+]], -15124; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]]125 126define void @test_v16i8_pos_odd(ptr %P, ptr %S) {127 %p = load %v16i8, ptr %P128 %r = add %v16i8 %p, < i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17 >129 store %v16i8 %r, ptr %S130 ret void131}132 133; CHECK-LABEL: test_v16i8_pos_odd:134; CHECK: vspltisb [[REG2:[0-9]+]], -16135; CHECK: vspltisb [[REG1:[0-9]+]], 1136; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]]137 138define void @test_v16i8_neg_odd(ptr %P, ptr %S) {139 %p = load %v16i8, ptr %P140 %r = add %v16i8 %p, < i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17 >141 store %v16i8 %r, ptr %S142 ret void143}144 145; CHECK-LABEL: test_v16i8_neg_odd:146; CHECK: vspltisb [[REG2:[0-9]+]], -16147; CHECK: vspltisb [[REG1:[0-9]+]], -1148; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG2]]149 150