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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-late-peephole=true < %s | FileCheck %s3; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \4; RUN: --check-prefix=CHECK-BE5; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \6; RUN: --check-prefix=CHECK-P77 8; Function Attrs: norecurse nounwind readnone9define zeroext i32 @geti(<4 x i32> %a, i32 zeroext %b) {10; CHECK-LABEL: geti:11; CHECK: # %bb.0: # %entry12; CHECK-NEXT: li 3, 213; CHECK-NEXT: andc 3, 3, 514; CHECK-NEXT: sldi 3, 3, 215; CHECK-NEXT: lvsl 3, 0, 316; CHECK-NEXT: li 3, 117; CHECK-NEXT: and 3, 3, 518; CHECK-NEXT: sldi 3, 3, 519; CHECK-NEXT: vperm 2, 2, 2, 320; CHECK-NEXT: mfvsrd 4, 3421; CHECK-NEXT: srd 3, 4, 322; CHECK-NEXT: clrldi 3, 3, 3223; CHECK-NEXT: blr24;25; CHECK-BE-LABEL: geti:26; CHECK-BE: # %bb.0: # %entry27; CHECK-BE-NEXT: andi. 3, 5, 228; CHECK-BE-NEXT: sldi 3, 3, 229; CHECK-BE-NEXT: lvsl 3, 0, 330; CHECK-BE-NEXT: li 3, 131; CHECK-BE-NEXT: andc 3, 3, 532; CHECK-BE-NEXT: sldi 3, 3, 533; CHECK-BE-NEXT: vperm 2, 2, 2, 334; CHECK-BE-NEXT: mfvsrd 4, 3435; CHECK-BE-NEXT: srd 3, 4, 336; CHECK-BE-NEXT: clrldi 3, 3, 3237; CHECK-BE-NEXT: blr38;39; CHECK-P7-LABEL: geti:40; CHECK-P7: # %bb.0: # %entry41; CHECK-P7-NEXT: addi 4, 1, -1642; CHECK-P7-NEXT: rlwinm 3, 5, 2, 28, 2943; CHECK-P7-NEXT: stxvw4x 34, 0, 444; CHECK-P7-NEXT: lwzx 3, 4, 345; CHECK-P7-NEXT: blr46entry:47 %vecext = extractelement <4 x i32> %a, i32 %b48 ret i32 %vecext49}50 51; Function Attrs: norecurse nounwind readnone52define i64 @getl(<2 x i64> %a, i32 zeroext %b) {53; CHECK-LABEL: getl:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: li 3, 156; CHECK-NEXT: andc 3, 3, 557; CHECK-NEXT: sldi 3, 3, 358; CHECK-NEXT: lvsl 3, 0, 359; CHECK-NEXT: vperm 2, 2, 2, 360; CHECK-NEXT: mfvsrd 3, 3461; CHECK-NEXT: blr62;63; CHECK-BE-LABEL: getl:64; CHECK-BE: # %bb.0: # %entry65; CHECK-BE-NEXT: andi. 3, 5, 166; CHECK-BE-NEXT: sldi 3, 3, 367; CHECK-BE-NEXT: lvsl 3, 0, 368; CHECK-BE-NEXT: vperm 2, 2, 2, 369; CHECK-BE-NEXT: mfvsrd 3, 3470; CHECK-BE-NEXT: blr71;72; CHECK-P7-LABEL: getl:73; CHECK-P7: # %bb.0: # %entry74; CHECK-P7-NEXT: addi 4, 1, -1675; CHECK-P7-NEXT: rlwinm 3, 5, 3, 28, 2876; CHECK-P7-NEXT: stxvd2x 34, 0, 477; CHECK-P7-NEXT: ldx 3, 4, 378; CHECK-P7-NEXT: blr79entry:80 %vecext = extractelement <2 x i64> %a, i32 %b81 ret i64 %vecext82}83 84; Function Attrs: norecurse nounwind readnone85define float @getf(<4 x float> %a, i32 zeroext %b) {86; CHECK-LABEL: getf:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: xori 3, 5, 389; CHECK-NEXT: sldi 3, 3, 290; CHECK-NEXT: lvsl 3, 0, 391; CHECK-NEXT: vperm 2, 2, 2, 392; CHECK-NEXT: xscvspdpn 1, 3493; CHECK-NEXT: blr94;95; CHECK-BE-LABEL: getf:96; CHECK-BE: # %bb.0: # %entry97; CHECK-BE-NEXT: sldi 3, 5, 298; CHECK-BE-NEXT: lvsl 3, 0, 399; CHECK-BE-NEXT: vperm 2, 2, 2, 3100; CHECK-BE-NEXT: xscvspdpn 1, 34101; CHECK-BE-NEXT: blr102;103; CHECK-P7-LABEL: getf:104; CHECK-P7: # %bb.0: # %entry105; CHECK-P7-NEXT: addi 4, 1, -16106; CHECK-P7-NEXT: rlwinm 3, 5, 2, 28, 29107; CHECK-P7-NEXT: stxvw4x 34, 0, 4108; CHECK-P7-NEXT: lfsx 1, 4, 3109; CHECK-P7-NEXT: blr110entry:111 %vecext = extractelement <4 x float> %a, i32 %b112 ret float %vecext113}114 115; Function Attrs: norecurse nounwind readnone116define double @getd(<2 x double> %a, i32 zeroext %b) {117; CHECK-LABEL: getd:118; CHECK: # %bb.0: # %entry119; CHECK-NEXT: li 3, 1120; CHECK-NEXT: andc 3, 3, 5121; CHECK-NEXT: sldi 3, 3, 3122; CHECK-NEXT: lvsl 3, 0, 3123; CHECK-NEXT: vperm 2, 2, 2, 3124; CHECK-NEXT: xxlor 1, 34, 34125; CHECK-NEXT: blr126;127; CHECK-BE-LABEL: getd:128; CHECK-BE: # %bb.0: # %entry129; CHECK-BE-NEXT: andi. 3, 5, 1130; CHECK-BE-NEXT: sldi 3, 3, 3131; CHECK-BE-NEXT: lvsl 3, 0, 3132; CHECK-BE-NEXT: vperm 2, 2, 2, 3133; CHECK-BE-NEXT: xxlor 1, 34, 34134; CHECK-BE-NEXT: blr135;136; CHECK-P7-LABEL: getd:137; CHECK-P7: # %bb.0: # %entry138; CHECK-P7-NEXT: andi. 3, 5, 1139; CHECK-P7-NEXT: sldi 3, 3, 3140; CHECK-P7-NEXT: lvsl 3, 0, 3141; CHECK-P7-NEXT: vperm 2, 2, 2, 3142; CHECK-P7-NEXT: xxlor 1, 34, 34143; CHECK-P7-NEXT: blr144entry:145 %vecext = extractelement <2 x double> %a, i32 %b146 ret double %vecext147}148