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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s3; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-P7 %s5define <8 x i16> @test_v8i16(<8 x i16> %m, <8 x i16> %n) {6; CHECK-P9-LABEL: test_v8i16:7; CHECK-P9: # %bb.0: # %entry8; CHECK-P9-NEXT: vavguh 2, 3, 29; CHECK-P9-NEXT: blr10;11; CHECK-P8-LABEL: test_v8i16:12; CHECK-P8: # %bb.0: # %entry13; CHECK-P8-NEXT: vavguh 2, 3, 214; CHECK-P8-NEXT: blr15;16; CHECK-P7-LABEL: test_v8i16:17; CHECK-P7: # %bb.0: # %entry18; CHECK-P7-NEXT: vavguh 2, 3, 219; CHECK-P7-NEXT: blr20entry:21 %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>22 %add1 = add <8 x i16> %add, %n23 %shr = lshr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>24 ret <8 x i16> %shr25}26 27define <8 x i16> @test_v8i16_sign(<8 x i16> %m, <8 x i16> %n) {28; CHECK-P9-LABEL: test_v8i16_sign:29; CHECK-P9: # %bb.0: # %entry30; CHECK-P9-NEXT: vavgsh 2, 3, 231; CHECK-P9-NEXT: blr32;33; CHECK-P8-LABEL: test_v8i16_sign:34; CHECK-P8: # %bb.0: # %entry35; CHECK-P8-NEXT: vavgsh 2, 3, 236; CHECK-P8-NEXT: blr37;38; CHECK-P7-LABEL: test_v8i16_sign:39; CHECK-P7: # %bb.0: # %entry40; CHECK-P7-NEXT: vavgsh 2, 3, 241; CHECK-P7-NEXT: blr42entry:43 %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>44 %add1 = add <8 x i16> %add, %n45 %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>46 ret <8 x i16> %shr47}48 49define <4 x i32> @test_v4i32(<4 x i32> %m, <4 x i32> %n) {50; CHECK-P9-LABEL: test_v4i32:51; CHECK-P9: # %bb.0: # %entry52; CHECK-P9-NEXT: vavguw 2, 3, 253; CHECK-P9-NEXT: blr54;55; CHECK-P8-LABEL: test_v4i32:56; CHECK-P8: # %bb.0: # %entry57; CHECK-P8-NEXT: vavguw 2, 3, 258; CHECK-P8-NEXT: blr59;60; CHECK-P7-LABEL: test_v4i32:61; CHECK-P7: # %bb.0: # %entry62; CHECK-P7-NEXT: vavguw 2, 3, 263; CHECK-P7-NEXT: blr64entry:65 %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>66 %add1 = add <4 x i32> %add, %n67 %shr = lshr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>68 ret <4 x i32> %shr69}70 71define <4 x i32> @test_v4i32_sign(<4 x i32> %m, <4 x i32> %n) {72; CHECK-P9-LABEL: test_v4i32_sign:73; CHECK-P9: # %bb.0: # %entry74; CHECK-P9-NEXT: vavgsw 2, 3, 275; CHECK-P9-NEXT: blr76;77; CHECK-P8-LABEL: test_v4i32_sign:78; CHECK-P8: # %bb.0: # %entry79; CHECK-P8-NEXT: vavgsw 2, 3, 280; CHECK-P8-NEXT: blr81;82; CHECK-P7-LABEL: test_v4i32_sign:83; CHECK-P7: # %bb.0: # %entry84; CHECK-P7-NEXT: vavgsw 2, 3, 285; CHECK-P7-NEXT: blr86entry:87 %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>88 %add1 = add <4 x i32> %add, %n89 %shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>90 ret <4 x i32> %shr91}92 93define <16 x i8> @test_v16i8(<16 x i8> %m, <16 x i8> %n) {94; CHECK-P9-LABEL: test_v16i8:95; CHECK-P9: # %bb.0: # %entry96; CHECK-P9-NEXT: vavgub 2, 3, 297; CHECK-P9-NEXT: blr98;99; CHECK-P8-LABEL: test_v16i8:100; CHECK-P8: # %bb.0: # %entry101; CHECK-P8-NEXT: vavgub 2, 3, 2102; CHECK-P8-NEXT: blr103;104; CHECK-P7-LABEL: test_v16i8:105; CHECK-P7: # %bb.0: # %entry106; CHECK-P7-NEXT: vavgub 2, 3, 2107; CHECK-P7-NEXT: blr108entry:109 %add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>110 %add1 = add <16 x i8> %add, %n111 %shr = lshr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>112 ret <16 x i8> %shr113}114 115define <16 x i8> @test_v16i8_sign(<16 x i8> %m, <16 x i8> %n) {116; CHECK-P9-LABEL: test_v16i8_sign:117; CHECK-P9: # %bb.0: # %entry118; CHECK-P9-NEXT: vavgsb 2, 3, 2119; CHECK-P9-NEXT: blr120;121; CHECK-P8-LABEL: test_v16i8_sign:122; CHECK-P8: # %bb.0: # %entry123; CHECK-P8-NEXT: vavgsb 2, 3, 2124; CHECK-P8-NEXT: blr125;126; CHECK-P7-LABEL: test_v16i8_sign:127; CHECK-P7: # %bb.0: # %entry128; CHECK-P7-NEXT: vavgsb 2, 3, 2129; CHECK-P7-NEXT: blr130entry:131 %add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>132 %add1 = add <16 x i8> %add, %n133 %shr = ashr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>134 ret <16 x i8> %shr135}136 137define <8 x i16> @test_v8i16_sign_negative(<8 x i16> %m, <8 x i16> %n) {138; CHECK-P9-LABEL: test_v8i16_sign_negative:139; CHECK-P9: # %bb.0: # %entry140; CHECK-P9-NEXT: addis 3, 2, .LCPI6_0@toc@ha141; CHECK-P9-NEXT: vadduhm 2, 2, 3142; CHECK-P9-NEXT: addi 3, 3, .LCPI6_0@toc@l143; CHECK-P9-NEXT: lxv 35, 0(3)144; CHECK-P9-NEXT: vadduhm 2, 2, 3145; CHECK-P9-NEXT: vspltish 3, 1146; CHECK-P9-NEXT: vsrah 2, 2, 3147; CHECK-P9-NEXT: blr148;149; CHECK-P8-LABEL: test_v8i16_sign_negative:150; CHECK-P8: # %bb.0: # %entry151; CHECK-P8-NEXT: addis 3, 2, .LCPI6_0@toc@ha152; CHECK-P8-NEXT: vadduhm 2, 2, 3153; CHECK-P8-NEXT: vspltish 5, 1154; CHECK-P8-NEXT: addi 3, 3, .LCPI6_0@toc@l155; CHECK-P8-NEXT: lxvd2x 0, 0, 3156; CHECK-P8-NEXT: xxswapd 36, 0157; CHECK-P8-NEXT: vadduhm 2, 2, 4158; CHECK-P8-NEXT: vsrah 2, 2, 5159; CHECK-P8-NEXT: blr160;161; CHECK-P7-LABEL: test_v8i16_sign_negative:162; CHECK-P7: # %bb.0: # %entry163; CHECK-P7-NEXT: addis 3, 2, .LCPI6_0@toc@ha164; CHECK-P7-NEXT: vadduhm 2, 2, 3165; CHECK-P7-NEXT: addi 3, 3, .LCPI6_0@toc@l166; CHECK-P7-NEXT: vspltish 5, 1167; CHECK-P7-NEXT: lxvd2x 0, 0, 3168; CHECK-P7-NEXT: xxswapd 36, 0169; CHECK-P7-NEXT: vadduhm 2, 2, 4170; CHECK-P7-NEXT: vsrah 2, 2, 5171; CHECK-P7-NEXT: blr172entry:173 %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 -1, i16 1, i16 1, i16 1, i16 1>174 %add1 = add <8 x i16> %add, %n175 %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>176 ret <8 x i16> %shr177}178 179define <4 x i32> @test_v4i32_negative(<4 x i32> %m, <4 x i32> %n) {180; CHECK-P9-LABEL: test_v4i32_negative:181; CHECK-P9: # %bb.0: # %entry182; CHECK-P9-NEXT: xxlnor 34, 34, 34183; CHECK-P9-NEXT: vsubuwm 2, 3, 2184; CHECK-P9-NEXT: vspltisw 3, 2185; CHECK-P9-NEXT: vsrw 2, 2, 3186; CHECK-P9-NEXT: blr187;188; CHECK-P8-LABEL: test_v4i32_negative:189; CHECK-P8: # %bb.0: # %entry190; CHECK-P8-NEXT: xxlnor 34, 34, 34191; CHECK-P8-NEXT: vspltisw 4, 2192; CHECK-P8-NEXT: vsubuwm 2, 3, 2193; CHECK-P8-NEXT: vsrw 2, 2, 4194; CHECK-P8-NEXT: blr195;196; CHECK-P7-LABEL: test_v4i32_negative:197; CHECK-P7: # %bb.0: # %entry198; CHECK-P7-NEXT: xxlnor 34, 34, 34199; CHECK-P7-NEXT: vspltisw 4, 2200; CHECK-P7-NEXT: vsubuwm 2, 3, 2201; CHECK-P7-NEXT: vsrw 2, 2, 4202; CHECK-P7-NEXT: blr203entry:204 %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>205 %add1 = add <4 x i32> %add, %n206 %shr = lshr <4 x i32> %add1, <i32 2, i32 2, i32 2, i32 2>207 ret <4 x i32> %shr208}209 210define <4 x i32> @test_v4i32_sign_negative(<4 x i32> %m, <4 x i32> %n) {211; CHECK-P9-LABEL: test_v4i32_sign_negative:212; CHECK-P9: # %bb.0: # %entry213; CHECK-P9-NEXT: vadduwm 2, 2, 3214; CHECK-P9-NEXT: xxleqv 35, 35, 35215; CHECK-P9-NEXT: vadduwm 2, 2, 3216; CHECK-P9-NEXT: vspltisw 3, 1217; CHECK-P9-NEXT: vsraw 2, 2, 3218; CHECK-P9-NEXT: blr219;220; CHECK-P8-LABEL: test_v4i32_sign_negative:221; CHECK-P8: # %bb.0: # %entry222; CHECK-P8-NEXT: vadduwm 2, 2, 3223; CHECK-P8-NEXT: xxleqv 35, 35, 35224; CHECK-P8-NEXT: vspltisw 4, 1225; CHECK-P8-NEXT: vadduwm 2, 2, 3226; CHECK-P8-NEXT: vsraw 2, 2, 4227; CHECK-P8-NEXT: blr228;229; CHECK-P7-LABEL: test_v4i32_sign_negative:230; CHECK-P7: # %bb.0: # %entry231; CHECK-P7-NEXT: vspltisb 4, -1232; CHECK-P7-NEXT: vadduwm 2, 2, 3233; CHECK-P7-NEXT: vspltisw 5, 1234; CHECK-P7-NEXT: vadduwm 2, 2, 4235; CHECK-P7-NEXT: vsraw 2, 2, 5236; CHECK-P7-NEXT: blr237entry:238 %add = add <4 x i32> %m, <i32 -1, i32 -1, i32 -1, i32 -1>239 %add1 = add <4 x i32> %add, %n240 %shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>241 ret <4 x i32> %shr242}243