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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s --check-prefix=CHECK-P85; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \7; RUN: FileCheck %s --check-prefix=CHECK-P98; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \9; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \10; RUN: FileCheck %s --check-prefix=CHECK-BE11 12define void @test8(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {13; CHECK-P8-LABEL: test8:14; CHECK-P8: # %bb.0: # %entry15; CHECK-P8-NEXT: lxvd2x vs0, 0, r416; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha17; CHECK-P8-NEXT: xxlxor v1, v1, v118; CHECK-P8-NEXT: addi r4, r4, .LCPI0_0@toc@l19; CHECK-P8-NEXT: lxvd2x vs1, 0, r420; CHECK-P8-NEXT: addis r4, r2, .LCPI0_1@toc@ha21; CHECK-P8-NEXT: addi r4, r4, .LCPI0_1@toc@l22; CHECK-P8-NEXT: lxvd2x vs2, 0, r423; CHECK-P8-NEXT: addis r4, r2, .LCPI0_3@toc@ha24; CHECK-P8-NEXT: addi r4, r4, .LCPI0_3@toc@l25; CHECK-P8-NEXT: lxvd2x vs3, 0, r426; CHECK-P8-NEXT: addis r4, r2, .LCPI0_2@toc@ha27; CHECK-P8-NEXT: addi r4, r4, .LCPI0_2@toc@l28; CHECK-P8-NEXT: xxswapd v2, vs029; CHECK-P8-NEXT: lxvd2x vs0, 0, r430; CHECK-P8-NEXT: li r4, 4831; CHECK-P8-NEXT: xxswapd v4, vs132; CHECK-P8-NEXT: vperm v4, v1, v2, v433; CHECK-P8-NEXT: xxswapd v5, vs234; CHECK-P8-NEXT: vperm v5, v1, v2, v535; CHECK-P8-NEXT: xvcvuxddp vs1, v536; CHECK-P8-NEXT: xxswapd v3, vs337; CHECK-P8-NEXT: vperm v3, v1, v2, v338; CHECK-P8-NEXT: xvcvuxddp vs2, v339; CHECK-P8-NEXT: xxswapd v0, vs040; CHECK-P8-NEXT: xvcvuxddp vs0, v441; CHECK-P8-NEXT: vperm v2, v1, v2, v042; CHECK-P8-NEXT: xxswapd vs1, vs143; CHECK-P8-NEXT: xvcvuxddp vs3, v244; CHECK-P8-NEXT: xxswapd vs2, vs245; CHECK-P8-NEXT: xxswapd vs0, vs046; CHECK-P8-NEXT: stxvd2x vs2, r3, r447; CHECK-P8-NEXT: li r4, 3248; CHECK-P8-NEXT: stxvd2x vs0, 0, r349; CHECK-P8-NEXT: xxswapd vs3, vs350; CHECK-P8-NEXT: stxvd2x vs3, r3, r451; CHECK-P8-NEXT: li r4, 1652; CHECK-P8-NEXT: stxvd2x vs1, r3, r453; CHECK-P8-NEXT: blr54;55; CHECK-P9-LABEL: test8:56; CHECK-P9: # %bb.0: # %entry57; CHECK-P9-NEXT: lxv v2, 0(r4)58; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0@toc@ha59; CHECK-P9-NEXT: xxlxor v4, v4, v460; CHECK-P9-NEXT: addi r4, r4, .LCPI0_0@toc@l61; CHECK-P9-NEXT: lxv v3, 0(r4)62; CHECK-P9-NEXT: addis r4, r2, .LCPI0_1@toc@ha63; CHECK-P9-NEXT: addi r4, r4, .LCPI0_1@toc@l64; CHECK-P9-NEXT: vperm v3, v4, v2, v365; CHECK-P9-NEXT: xvcvuxddp vs0, v366; CHECK-P9-NEXT: lxv v3, 0(r4)67; CHECK-P9-NEXT: addis r4, r2, .LCPI0_2@toc@ha68; CHECK-P9-NEXT: addi r4, r4, .LCPI0_2@toc@l69; CHECK-P9-NEXT: vperm v3, v4, v2, v370; CHECK-P9-NEXT: stxv vs0, 0(r3)71; CHECK-P9-NEXT: xvcvuxddp vs1, v372; CHECK-P9-NEXT: lxv v3, 0(r4)73; CHECK-P9-NEXT: addis r4, r2, .LCPI0_3@toc@ha74; CHECK-P9-NEXT: addi r4, r4, .LCPI0_3@toc@l75; CHECK-P9-NEXT: vperm v3, v4, v2, v376; CHECK-P9-NEXT: stxv vs1, 16(r3)77; CHECK-P9-NEXT: xvcvuxddp vs2, v378; CHECK-P9-NEXT: lxv v3, 0(r4)79; CHECK-P9-NEXT: vperm v2, v4, v2, v380; CHECK-P9-NEXT: stxv vs2, 32(r3)81; CHECK-P9-NEXT: xvcvuxddp vs3, v282; CHECK-P9-NEXT: stxv vs3, 48(r3)83; CHECK-P9-NEXT: blr84;85; CHECK-BE-LABEL: test8:86; CHECK-BE: # %bb.0: # %entry87; CHECK-BE-NEXT: lxv v2, 0(r4)88; CHECK-BE-NEXT: addis r4, r2, .LCPI0_0@toc@ha89; CHECK-BE-NEXT: xxlxor v4, v4, v490; CHECK-BE-NEXT: addi r4, r4, .LCPI0_0@toc@l91; CHECK-BE-NEXT: lxv v3, 0(r4)92; CHECK-BE-NEXT: addis r4, r2, .LCPI0_1@toc@ha93; CHECK-BE-NEXT: addi r4, r4, .LCPI0_1@toc@l94; CHECK-BE-NEXT: vperm v3, v4, v2, v395; CHECK-BE-NEXT: xvcvuxddp vs0, v396; CHECK-BE-NEXT: lxv v3, 0(r4)97; CHECK-BE-NEXT: addis r4, r2, .LCPI0_2@toc@ha98; CHECK-BE-NEXT: addi r4, r4, .LCPI0_2@toc@l99; CHECK-BE-NEXT: vperm v3, v4, v2, v3100; CHECK-BE-NEXT: stxv vs0, 0(r3)101; CHECK-BE-NEXT: xvcvuxddp vs1, v3102; CHECK-BE-NEXT: lxv v3, 0(r4)103; CHECK-BE-NEXT: addis r4, r2, .LCPI0_3@toc@ha104; CHECK-BE-NEXT: addi r4, r4, .LCPI0_3@toc@l105; CHECK-BE-NEXT: vperm v3, v4, v2, v3106; CHECK-BE-NEXT: stxv vs1, 16(r3)107; CHECK-BE-NEXT: xvcvuxddp vs2, v3108; CHECK-BE-NEXT: lxv v3, 0(r4)109; CHECK-BE-NEXT: vperm v2, v4, v2, v3110; CHECK-BE-NEXT: stxv vs2, 32(r3)111; CHECK-BE-NEXT: xvcvuxddp vs3, v2112; CHECK-BE-NEXT: stxv vs3, 48(r3)113; CHECK-BE-NEXT: blr114entry:115 %0 = load <8 x i16>, ptr %SrcPtr, align 16116 %1 = uitofp <8 x i16> %0 to <8 x double>117 store <8 x double> %1, ptr %Sink, align 16118 ret void119}120 121define void @test4(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {122; CHECK-P8-LABEL: test4:123; CHECK-P8: # %bb.0: # %entry124; CHECK-P8-NEXT: lxvd2x vs0, 0, r4125; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha126; CHECK-P8-NEXT: xxlxor v5, v5, v5127; CHECK-P8-NEXT: addi r4, r4, .LCPI1_0@toc@l128; CHECK-P8-NEXT: lxvd2x vs1, 0, r4129; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha130; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l131; CHECK-P8-NEXT: xxswapd v2, vs0132; CHECK-P8-NEXT: lxvd2x vs0, 0, r4133; CHECK-P8-NEXT: li r4, 16134; CHECK-P8-NEXT: xxswapd v3, vs1135; CHECK-P8-NEXT: vperm v3, v5, v2, v3136; CHECK-P8-NEXT: xxswapd v4, vs0137; CHECK-P8-NEXT: xvcvuxddp vs0, v3138; CHECK-P8-NEXT: vperm v2, v5, v2, v4139; CHECK-P8-NEXT: xvcvuxddp vs1, v2140; CHECK-P8-NEXT: xxswapd vs0, vs0141; CHECK-P8-NEXT: stxvd2x vs0, 0, r3142; CHECK-P8-NEXT: xxswapd vs1, vs1143; CHECK-P8-NEXT: stxvd2x vs1, r3, r4144; CHECK-P8-NEXT: blr145;146; CHECK-P9-LABEL: test4:147; CHECK-P9: # %bb.0: # %entry148; CHECK-P9-NEXT: lxv v2, 0(r4)149; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha150; CHECK-P9-NEXT: xxlxor v4, v4, v4151; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l152; CHECK-P9-NEXT: lxv v3, 0(r4)153; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha154; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l155; CHECK-P9-NEXT: vperm v3, v4, v2, v3156; CHECK-P9-NEXT: xvcvuxddp vs0, v3157; CHECK-P9-NEXT: lxv v3, 0(r4)158; CHECK-P9-NEXT: vperm v2, v4, v2, v3159; CHECK-P9-NEXT: stxv vs0, 0(r3)160; CHECK-P9-NEXT: xvcvuxddp vs1, v2161; CHECK-P9-NEXT: stxv vs1, 16(r3)162; CHECK-P9-NEXT: blr163;164; CHECK-BE-LABEL: test4:165; CHECK-BE: # %bb.0: # %entry166; CHECK-BE-NEXT: lxv v2, 0(r4)167; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha168; CHECK-BE-NEXT: xxlxor v4, v4, v4169; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l170; CHECK-BE-NEXT: lxv v3, 0(r4)171; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha172; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l173; CHECK-BE-NEXT: vperm v3, v4, v2, v3174; CHECK-BE-NEXT: xvcvuxddp vs0, v3175; CHECK-BE-NEXT: lxv v3, 0(r4)176; CHECK-BE-NEXT: vperm v2, v4, v2, v3177; CHECK-BE-NEXT: stxv vs0, 0(r3)178; CHECK-BE-NEXT: xvcvuxddp vs1, v2179; CHECK-BE-NEXT: stxv vs1, 16(r3)180; CHECK-BE-NEXT: blr181entry:182 %0 = load <4 x i16>, ptr %SrcPtr, align 16183 %1 = uitofp <4 x i16> %0 to <4 x double>184 store <4 x double> %1, ptr %Sink, align 16185 ret void186}187 188define void @test2(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {189; CHECK-P8-LABEL: test2:190; CHECK-P8: # %bb.0: # %entry191; CHECK-P8-NEXT: lxvd2x vs0, 0, r4192; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha193; CHECK-P8-NEXT: xxlxor v4, v4, v4194; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l195; CHECK-P8-NEXT: xxswapd v2, vs0196; CHECK-P8-NEXT: lxvd2x vs0, 0, r4197; CHECK-P8-NEXT: xxswapd v3, vs0198; CHECK-P8-NEXT: vperm v2, v4, v2, v3199; CHECK-P8-NEXT: xvcvuxddp vs0, v2200; CHECK-P8-NEXT: xxswapd vs0, vs0201; CHECK-P8-NEXT: stxvd2x vs0, 0, r3202; CHECK-P8-NEXT: blr203;204; CHECK-P9-LABEL: test2:205; CHECK-P9: # %bb.0: # %entry206; CHECK-P9-NEXT: lxv vs0, 0(r4)207; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha208; CHECK-P9-NEXT: xxlxor vs2, vs2, vs2209; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l210; CHECK-P9-NEXT: lxv vs1, 0(r4)211; CHECK-P9-NEXT: xxperm vs0, vs2, vs1212; CHECK-P9-NEXT: xvcvuxddp vs0, vs0213; CHECK-P9-NEXT: stxv vs0, 0(r3)214; CHECK-P9-NEXT: blr215;216; CHECK-BE-LABEL: test2:217; CHECK-BE: # %bb.0: # %entry218; CHECK-BE-NEXT: lxv v2, 0(r4)219; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha220; CHECK-BE-NEXT: xxlxor v4, v4, v4221; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l222; CHECK-BE-NEXT: lxv v3, 0(r4)223; CHECK-BE-NEXT: vperm v2, v4, v2, v3224; CHECK-BE-NEXT: xvcvuxddp vs0, v2225; CHECK-BE-NEXT: stxv vs0, 0(r3)226; CHECK-BE-NEXT: blr227entry:228 %0 = load <2 x i16>, ptr %SrcPtr, align 16229 %1 = uitofp <2 x i16> %0 to <2 x double>230 store <2 x double> %1, ptr %Sink, align 16231 ret void232}233 234define void @stest8(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {235; CHECK-P8-LABEL: stest8:236; CHECK-P8: # %bb.0: # %entry237; CHECK-P8-NEXT: lxvd2x vs0, 0, r4238; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha239; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l240; CHECK-P8-NEXT: lxvd2x vs1, 0, r4241; CHECK-P8-NEXT: addis r4, r2, .LCPI3_2@toc@ha242; CHECK-P8-NEXT: addi r4, r4, .LCPI3_2@toc@l243; CHECK-P8-NEXT: lxvd2x vs2, 0, r4244; CHECK-P8-NEXT: addis r4, r2, .LCPI3_4@toc@ha245; CHECK-P8-NEXT: addi r4, r4, .LCPI3_4@toc@l246; CHECK-P8-NEXT: lxvd2x vs3, 0, r4247; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha248; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l249; CHECK-P8-NEXT: xxswapd v2, vs0250; CHECK-P8-NEXT: lxvd2x vs0, 0, r4251; CHECK-P8-NEXT: addis r4, r2, .LCPI3_1@toc@ha252; CHECK-P8-NEXT: addi r4, r4, .LCPI3_1@toc@l253; CHECK-P8-NEXT: xxswapd v4, vs1254; CHECK-P8-NEXT: vperm v4, v2, v2, v4255; CHECK-P8-NEXT: xxswapd v5, vs2256; CHECK-P8-NEXT: vperm v5, v2, v2, v5257; CHECK-P8-NEXT: xxswapd v3, vs3258; CHECK-P8-NEXT: vperm v3, v2, v2, v3259; CHECK-P8-NEXT: xxswapd v0, vs0260; CHECK-P8-NEXT: vperm v2, v2, v2, v0261; CHECK-P8-NEXT: lxvd2x v0, 0, r4262; CHECK-P8-NEXT: li r4, 48263; CHECK-P8-NEXT: vsld v3, v3, v0264; CHECK-P8-NEXT: vsld v2, v2, v0265; CHECK-P8-NEXT: vsld v4, v4, v0266; CHECK-P8-NEXT: vsld v5, v5, v0267; CHECK-P8-NEXT: vsrad v3, v3, v0268; CHECK-P8-NEXT: vsrad v2, v2, v0269; CHECK-P8-NEXT: vsrad v4, v4, v0270; CHECK-P8-NEXT: vsrad v5, v5, v0271; CHECK-P8-NEXT: xvcvsxddp vs2, v3272; CHECK-P8-NEXT: xvcvsxddp vs3, v2273; CHECK-P8-NEXT: xvcvsxddp vs0, v4274; CHECK-P8-NEXT: xvcvsxddp vs1, v5275; CHECK-P8-NEXT: xxswapd vs2, vs2276; CHECK-P8-NEXT: xxswapd vs3, vs3277; CHECK-P8-NEXT: xxswapd vs1, vs1278; CHECK-P8-NEXT: xxswapd vs0, vs0279; CHECK-P8-NEXT: stxvd2x vs2, r3, r4280; CHECK-P8-NEXT: li r4, 32281; CHECK-P8-NEXT: stxvd2x vs0, 0, r3282; CHECK-P8-NEXT: stxvd2x vs3, r3, r4283; CHECK-P8-NEXT: li r4, 16284; CHECK-P8-NEXT: stxvd2x vs1, r3, r4285; CHECK-P8-NEXT: blr286;287; CHECK-P9-LABEL: stest8:288; CHECK-P9: # %bb.0: # %entry289; CHECK-P9-NEXT: lxv v2, 0(r4)290; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha291; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l292; CHECK-P9-NEXT: lxv v3, 0(r4)293; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha294; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l295; CHECK-P9-NEXT: vperm v3, v2, v2, v3296; CHECK-P9-NEXT: vextsh2d v3, v3297; CHECK-P9-NEXT: xvcvsxddp vs0, v3298; CHECK-P9-NEXT: lxv v3, 0(r4)299; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha300; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l301; CHECK-P9-NEXT: vperm v3, v2, v2, v3302; CHECK-P9-NEXT: stxv vs0, 0(r3)303; CHECK-P9-NEXT: vextsh2d v3, v3304; CHECK-P9-NEXT: xvcvsxddp vs1, v3305; CHECK-P9-NEXT: lxv v3, 0(r4)306; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha307; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l308; CHECK-P9-NEXT: vperm v3, v2, v2, v3309; CHECK-P9-NEXT: stxv vs1, 16(r3)310; CHECK-P9-NEXT: vextsh2d v3, v3311; CHECK-P9-NEXT: xvcvsxddp vs2, v3312; CHECK-P9-NEXT: lxv v3, 0(r4)313; CHECK-P9-NEXT: vperm v2, v2, v2, v3314; CHECK-P9-NEXT: stxv vs2, 32(r3)315; CHECK-P9-NEXT: vextsh2d v2, v2316; CHECK-P9-NEXT: xvcvsxddp vs3, v2317; CHECK-P9-NEXT: stxv vs3, 48(r3)318; CHECK-P9-NEXT: blr319;320; CHECK-BE-LABEL: stest8:321; CHECK-BE: # %bb.0: # %entry322; CHECK-BE-NEXT: lxv v2, 0(r4)323; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha324; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l325; CHECK-BE-NEXT: lxv v3, 0(r4)326; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha327; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l328; CHECK-BE-NEXT: vperm v3, v2, v2, v3329; CHECK-BE-NEXT: vextsh2d v3, v3330; CHECK-BE-NEXT: xvcvsxddp vs0, v3331; CHECK-BE-NEXT: lxv v3, 0(r4)332; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha333; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l334; CHECK-BE-NEXT: vperm v3, v2, v2, v3335; CHECK-BE-NEXT: stxv vs0, 0(r3)336; CHECK-BE-NEXT: vextsh2d v3, v3337; CHECK-BE-NEXT: xvcvsxddp vs1, v3338; CHECK-BE-NEXT: lxv v3, 0(r4)339; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha340; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l341; CHECK-BE-NEXT: vperm v3, v2, v2, v3342; CHECK-BE-NEXT: stxv vs1, 16(r3)343; CHECK-BE-NEXT: vextsh2d v3, v3344; CHECK-BE-NEXT: xvcvsxddp vs2, v3345; CHECK-BE-NEXT: lxv v3, 0(r4)346; CHECK-BE-NEXT: vperm v2, v2, v2, v3347; CHECK-BE-NEXT: stxv vs2, 32(r3)348; CHECK-BE-NEXT: vextsh2d v2, v2349; CHECK-BE-NEXT: xvcvsxddp vs3, v2350; CHECK-BE-NEXT: stxv vs3, 48(r3)351; CHECK-BE-NEXT: blr352entry:353 %0 = load <8 x i16>, ptr %SrcPtr, align 16354 %1 = sitofp <8 x i16> %0 to <8 x double>355 store <8 x double> %1, ptr %Sink, align 16356 ret void357}358 359define void @stest4(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {360; CHECK-P8-LABEL: stest4:361; CHECK-P8: # %bb.0: # %entry362; CHECK-P8-NEXT: lxvd2x vs0, 0, r4363; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha364; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l365; CHECK-P8-NEXT: lxvd2x vs1, 0, r4366; CHECK-P8-NEXT: addis r4, r2, .LCPI4_2@toc@ha367; CHECK-P8-NEXT: addi r4, r4, .LCPI4_2@toc@l368; CHECK-P8-NEXT: xxswapd v2, vs0369; CHECK-P8-NEXT: lxvd2x vs0, 0, r4370; CHECK-P8-NEXT: addis r4, r2, .LCPI4_1@toc@ha371; CHECK-P8-NEXT: addi r4, r4, .LCPI4_1@toc@l372; CHECK-P8-NEXT: xxswapd v3, vs1373; CHECK-P8-NEXT: vperm v3, v2, v2, v3374; CHECK-P8-NEXT: xxswapd v4, vs0375; CHECK-P8-NEXT: vperm v2, v2, v2, v4376; CHECK-P8-NEXT: lxvd2x v4, 0, r4377; CHECK-P8-NEXT: li r4, 16378; CHECK-P8-NEXT: vsld v3, v3, v4379; CHECK-P8-NEXT: vsld v2, v2, v4380; CHECK-P8-NEXT: vsrad v3, v3, v4381; CHECK-P8-NEXT: vsrad v2, v2, v4382; CHECK-P8-NEXT: xvcvsxddp vs0, v3383; CHECK-P8-NEXT: xvcvsxddp vs1, v2384; CHECK-P8-NEXT: xxswapd vs1, vs1385; CHECK-P8-NEXT: xxswapd vs0, vs0386; CHECK-P8-NEXT: stxvd2x vs1, r3, r4387; CHECK-P8-NEXT: stxvd2x vs0, 0, r3388; CHECK-P8-NEXT: blr389;390; CHECK-P9-LABEL: stest4:391; CHECK-P9: # %bb.0: # %entry392; CHECK-P9-NEXT: lxv v2, 0(r4)393; CHECK-P9-NEXT: addis r4, r2, .LCPI4_0@toc@ha394; CHECK-P9-NEXT: addi r4, r4, .LCPI4_0@toc@l395; CHECK-P9-NEXT: lxv v3, 0(r4)396; CHECK-P9-NEXT: addis r4, r2, .LCPI4_1@toc@ha397; CHECK-P9-NEXT: addi r4, r4, .LCPI4_1@toc@l398; CHECK-P9-NEXT: vperm v3, v2, v2, v3399; CHECK-P9-NEXT: vextsh2d v3, v3400; CHECK-P9-NEXT: xvcvsxddp vs0, v3401; CHECK-P9-NEXT: lxv v3, 0(r4)402; CHECK-P9-NEXT: vperm v2, v2, v2, v3403; CHECK-P9-NEXT: stxv vs0, 0(r3)404; CHECK-P9-NEXT: vextsh2d v2, v2405; CHECK-P9-NEXT: xvcvsxddp vs1, v2406; CHECK-P9-NEXT: stxv vs1, 16(r3)407; CHECK-P9-NEXT: blr408;409; CHECK-BE-LABEL: stest4:410; CHECK-BE: # %bb.0: # %entry411; CHECK-BE-NEXT: lxv v2, 0(r4)412; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha413; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l414; CHECK-BE-NEXT: lxv v3, 0(r4)415; CHECK-BE-NEXT: addis r4, r2, .LCPI4_1@toc@ha416; CHECK-BE-NEXT: addi r4, r4, .LCPI4_1@toc@l417; CHECK-BE-NEXT: vperm v3, v2, v2, v3418; CHECK-BE-NEXT: vextsh2d v3, v3419; CHECK-BE-NEXT: xvcvsxddp vs0, v3420; CHECK-BE-NEXT: lxv v3, 0(r4)421; CHECK-BE-NEXT: vperm v2, v2, v2, v3422; CHECK-BE-NEXT: stxv vs0, 0(r3)423; CHECK-BE-NEXT: vextsh2d v2, v2424; CHECK-BE-NEXT: xvcvsxddp vs1, v2425; CHECK-BE-NEXT: stxv vs1, 16(r3)426; CHECK-BE-NEXT: blr427entry:428 %0 = load <4 x i16>, ptr %SrcPtr, align 16429 %1 = sitofp <4 x i16> %0 to <4 x double>430 store <4 x double> %1, ptr %Sink, align 16431 ret void432}433 434define void @stest2(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {435; CHECK-P8-LABEL: stest2:436; CHECK-P8: # %bb.0: # %entry437; CHECK-P8-NEXT: lxvd2x vs0, 0, r4438; CHECK-P8-NEXT: addis r4, r2, .LCPI5_0@toc@ha439; CHECK-P8-NEXT: addi r4, r4, .LCPI5_0@toc@l440; CHECK-P8-NEXT: xxswapd v2, vs0441; CHECK-P8-NEXT: lxvd2x vs0, 0, r4442; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha443; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l444; CHECK-P8-NEXT: xxswapd v3, vs0445; CHECK-P8-NEXT: vperm v2, v2, v2, v3446; CHECK-P8-NEXT: lxvd2x v3, 0, r4447; CHECK-P8-NEXT: vsld v2, v2, v3448; CHECK-P8-NEXT: vsrad v2, v2, v3449; CHECK-P8-NEXT: xvcvsxddp vs0, v2450; CHECK-P8-NEXT: xxswapd vs0, vs0451; CHECK-P8-NEXT: stxvd2x vs0, 0, r3452; CHECK-P8-NEXT: blr453;454; CHECK-P9-LABEL: stest2:455; CHECK-P9: # %bb.0: # %entry456; CHECK-P9-NEXT: lxv v2, 0(r4)457; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha458; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l459; CHECK-P9-NEXT: lxv vs0, 0(r4)460; CHECK-P9-NEXT: xxperm v2, v2, vs0461; CHECK-P9-NEXT: vextsh2d v2, v2462; CHECK-P9-NEXT: xvcvsxddp vs0, v2463; CHECK-P9-NEXT: stxv vs0, 0(r3)464; CHECK-P9-NEXT: blr465;466; CHECK-BE-LABEL: stest2:467; CHECK-BE: # %bb.0: # %entry468; CHECK-BE-NEXT: lxv v2, 0(r4)469; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha470; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l471; CHECK-BE-NEXT: lxv vs0, 0(r4)472; CHECK-BE-NEXT: xxperm v2, v2, vs0473; CHECK-BE-NEXT: vextsh2d v2, v2474; CHECK-BE-NEXT: xvcvsxddp vs0, v2475; CHECK-BE-NEXT: stxv vs0, 0(r3)476; CHECK-BE-NEXT: blr477entry:478 %0 = load <2 x i16>, ptr %SrcPtr, align 16479 %1 = sitofp <2 x i16> %0 to <2 x double>480 store <2 x double> %1, ptr %Sink, align 16481 ret void482}483