238 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,PWR83; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr7 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,PWR74 5define <16 x i8> @getsmaxi8(<16 x i8> %a, <16 x i8> %b) {6; CHECK-LABEL: getsmaxi8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vmaxsb 2, 2, 39; CHECK-NEXT: blr10entry:11 %0 = icmp sgt <16 x i8> %a, %b12 %1 = select <16 x i1> %0, <16 x i8> %a, <16 x i8> %b13 ret <16 x i8> %114}15 16define <8 x i16> @getsmaxi16(<8 x i16> %a, <8 x i16> %b) {17; CHECK-LABEL: getsmaxi16:18; CHECK: # %bb.0: # %entry19; CHECK-NEXT: vmaxsh 2, 2, 320; CHECK-NEXT: blr21entry:22 %0 = icmp sgt <8 x i16> %a, %b23 %1 = select <8 x i1> %0, <8 x i16> %a, <8 x i16> %b24 ret <8 x i16> %125}26 27define <4 x i32> @getsmaxi32(<4 x i32> %a, <4 x i32> %b) {28; CHECK-LABEL: getsmaxi32:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: vmaxsw 2, 2, 331; CHECK-NEXT: blr32entry:33 %0 = icmp sgt <4 x i32> %a, %b34 %1 = select <4 x i1> %0, <4 x i32> %a, <4 x i32> %b35 ret <4 x i32> %136}37 38define <2 x i64> @getsmaxi64(<2 x i64> %a, <2 x i64> %b) {39; PWR8-LABEL: getsmaxi64:40; PWR8: # %bb.0: # %entry41; PWR8-NEXT: vmaxsd 2, 2, 342; PWR8-NEXT: blr43;44; PWR7-LABEL: getsmaxi64:45; PWR7: # %bb.0: # %entry46; PWR7-NEXT: xxswapd 0, 3547; PWR7-NEXT: addi 3, 1, -3248; PWR7-NEXT: xxswapd 1, 3449; PWR7-NEXT: stxvd2x 0, 0, 350; PWR7-NEXT: addi 3, 1, -4851; PWR7-NEXT: stxvd2x 1, 0, 352; PWR7-NEXT: ld 3, -24(1)53; PWR7-NEXT: ld 4, -40(1)54; PWR7-NEXT: ld 6, -48(1)55; PWR7-NEXT: cmpd 4, 356; PWR7-NEXT: li 3, 057; PWR7-NEXT: li 4, -158; PWR7-NEXT: iselgt 5, 4, 359; PWR7-NEXT: std 5, -8(1)60; PWR7-NEXT: ld 5, -32(1)61; PWR7-NEXT: cmpd 6, 562; PWR7-NEXT: iselgt 3, 4, 363; PWR7-NEXT: std 3, -16(1)64; PWR7-NEXT: addi 3, 1, -1665; PWR7-NEXT: lxvd2x 0, 0, 366; PWR7-NEXT: xxswapd 36, 067; PWR7-NEXT: xxsel 34, 35, 34, 3668; PWR7-NEXT: blr69entry:70 %0 = icmp sgt <2 x i64> %a, %b71 %1 = select <2 x i1> %0, <2 x i64> %a, <2 x i64> %b72 ret <2 x i64> %173}74 75define <4 x float> @getsmaxf32(<4 x float> %a, <4 x float> %b) {76; CHECK-LABEL: getsmaxf32:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: xvmaxsp 34, 34, 3579; CHECK-NEXT: blr80entry:81 %0 = fcmp nnan nsz oge <4 x float> %a, %b82 %1 = select nsz <4 x i1> %0, <4 x float> %a, <4 x float> %b83 ret <4 x float> %184}85 86define <2 x double> @getsmaxf64(<2 x double> %a, <2 x double> %b) {87; CHECK-LABEL: getsmaxf64:88; CHECK: # %bb.0: # %entry89; CHECK-NEXT: xvmaxdp 34, 34, 3590; CHECK-NEXT: blr91entry:92 %0 = fcmp nnan nsz oge <2 x double> %a, %b93 %1 = select nsz <2 x i1> %0, <2 x double> %a, <2 x double> %b94 ret <2 x double> %195}96 97define <16 x i8> @getsmini8(<16 x i8> %a, <16 x i8> %b) {98; CHECK-LABEL: getsmini8:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: vminsb 2, 2, 3101; CHECK-NEXT: blr102entry:103 %0 = icmp slt <16 x i8> %a, %b104 %1 = select <16 x i1> %0, <16 x i8> %a, <16 x i8> %b105 ret <16 x i8> %1106}107 108define <8 x i16> @getsmini16(<8 x i16> %a, <8 x i16> %b) {109; CHECK-LABEL: getsmini16:110; CHECK: # %bb.0: # %entry111; CHECK-NEXT: vminsh 2, 2, 3112; CHECK-NEXT: blr113entry:114 %0 = icmp slt <8 x i16> %a, %b115 %1 = select <8 x i1> %0, <8 x i16> %a, <8 x i16> %b116 ret <8 x i16> %1117}118 119define <4 x i32> @getsmini32(<4 x i32> %a, <4 x i32> %b) {120; CHECK-LABEL: getsmini32:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vminsw 2, 2, 3123; CHECK-NEXT: blr124entry:125 %0 = icmp slt <4 x i32> %a, %b126 %1 = select <4 x i1> %0, <4 x i32> %a, <4 x i32> %b127 ret <4 x i32> %1128}129 130define <2 x i64> @getsmini64(<2 x i64> %a, <2 x i64> %b) {131; PWR8-LABEL: getsmini64:132; PWR8: # %bb.0: # %entry133; PWR8-NEXT: vminsd 2, 2, 3134; PWR8-NEXT: blr135;136; PWR7-LABEL: getsmini64:137; PWR7: # %bb.0: # %entry138; PWR7-NEXT: xxswapd 0, 35139; PWR7-NEXT: addi 3, 1, -32140; PWR7-NEXT: xxswapd 1, 34141; PWR7-NEXT: stxvd2x 0, 0, 3142; PWR7-NEXT: addi 3, 1, -48143; PWR7-NEXT: stxvd2x 1, 0, 3144; PWR7-NEXT: ld 3, -24(1)145; PWR7-NEXT: ld 4, -40(1)146; PWR7-NEXT: ld 6, -48(1)147; PWR7-NEXT: cmpd 4, 3148; PWR7-NEXT: li 3, 0149; PWR7-NEXT: li 4, -1150; PWR7-NEXT: isellt 5, 4, 3151; PWR7-NEXT: std 5, -8(1)152; PWR7-NEXT: ld 5, -32(1)153; PWR7-NEXT: cmpd 6, 5154; PWR7-NEXT: isellt 3, 4, 3155; PWR7-NEXT: std 3, -16(1)156; PWR7-NEXT: addi 3, 1, -16157; PWR7-NEXT: lxvd2x 0, 0, 3158; PWR7-NEXT: xxswapd 36, 0159; PWR7-NEXT: xxsel 34, 35, 34, 36160; PWR7-NEXT: blr161entry:162 %0 = icmp slt <2 x i64> %a, %b163 %1 = select <2 x i1> %0, <2 x i64> %a, <2 x i64> %b164 ret <2 x i64> %1165}166 167define <4 x float> @getsminf32(<4 x float> %a, <4 x float> %b) {168; CHECK-LABEL: getsminf32:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: xvminsp 34, 34, 35171; CHECK-NEXT: blr172entry:173 %0 = fcmp nnan nsz ole <4 x float> %a, %b174 %1 = select nsz <4 x i1> %0, <4 x float> %a, <4 x float> %b175 ret <4 x float> %1176}177 178define <2 x double> @getsminf64(<2 x double> %a, <2 x double> %b) {179; CHECK-LABEL: getsminf64:180; CHECK: # %bb.0: # %entry181; CHECK-NEXT: xvmindp 34, 34, 35182; CHECK-NEXT: blr183entry:184 %0 = fcmp nnan nsz ole <2 x double> %a, %b185 %1 = select nsz <2 x i1> %0, <2 x double> %a, <2 x double> %b186 ret <2 x double> %1187}188 189define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {190; PWR8-LABEL: invalidv1i128:191; PWR8: # %bb.0:192; PWR8-NEXT: mfvsrd 3, 36193; PWR8-NEXT: mfvsrd 4, 34194; PWR8-NEXT: cmpld 4, 3195; PWR8-NEXT: xxswapd 0, 36196; PWR8-NEXT: xxswapd 1, 34197; PWR8-NEXT: cmpd 1, 4, 3198; PWR8-NEXT: mffprd 3, 0199; PWR8-NEXT: mffprd 4, 1200; PWR8-NEXT: crandc 20, 4, 2201; PWR8-NEXT: cmpld 1, 4, 3202; PWR8-NEXT: bc 12, 20, .LBB12_3203; PWR8-NEXT: # %bb.1:204; PWR8-NEXT: crand 20, 2, 4205; PWR8-NEXT: bc 12, 20, .LBB12_3206; PWR8-NEXT: # %bb.2:207; PWR8-NEXT: vmr 2, 4208; PWR8-NEXT: .LBB12_3:209; PWR8-NEXT: xxswapd 0, 34210; PWR8-NEXT: mfvsrd 4, 34211; PWR8-NEXT: mffprd 3, 0212; PWR8-NEXT: blr213;214; PWR7-LABEL: invalidv1i128:215; PWR7: # %bb.0:216; PWR7-NEXT: cmpld 4, 8217; PWR7-NEXT: cmpd 1, 4, 8218; PWR7-NEXT: crandc 20, 4, 2219; PWR7-NEXT: cmpld 1, 3, 7220; PWR7-NEXT: crand 21, 2, 4221; PWR7-NEXT: cror 20, 21, 20222; PWR7-NEXT: isel 3, 3, 7, 20223; PWR7-NEXT: isel 4, 4, 8, 20224; PWR7-NEXT: std 3, -32(1)225; PWR7-NEXT: addi 3, 1, -32226; PWR7-NEXT: std 4, -24(1)227; PWR7-NEXT: lxvd2x 0, 0, 3228; PWR7-NEXT: addi 3, 1, -16229; PWR7-NEXT: stxvd2x 0, 0, 3230; PWR7-NEXT: ld 3, -16(1)231; PWR7-NEXT: ld 4, -8(1)232; PWR7-NEXT: blr233%1 = icmp slt <2 x i128> %v1, %v2234%2 = select <2 x i1> %1, <2 x i128> %v1, <2 x i128> %v2235%3 = extractelement <2 x i128> %2, i32 0236ret i128 %3237}238