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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s4define dso_local <4 x i32> @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {5; CHECK-LABEL: test:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: xxsel vs34, vs34, vs35, vs368; CHECK-NEXT: blr9entry:10 %neg.i = xor <4 x i32> %c, <i32 -1, i32 -1, i32 -1, i32 -1>11 %and.i = and <4 x i32> %neg.i, %a12 %and1.i = and <4 x i32> %c, %b13 %or.i = or <4 x i32> %and1.i, %and.i14 ret <4 x i32> %or.i15}16 17define dso_local <8 x i16> @test2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {18; CHECK-LABEL: test2:19; CHECK: # %bb.0: # %entry20; CHECK-NEXT: xxsel vs34, vs34, vs35, vs3621; CHECK-NEXT: blr22entry:23 %neg.i = xor <8 x i16> %c, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>24 %and.i = and <8 x i16> %a, %neg.i25 %and1.i = and <8 x i16> %c, %b26 %or.i = or <8 x i16> %and.i, %and1.i27 ret <8 x i16> %or.i28}29 30define dso_local <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {31; CHECK-LABEL: test3:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: xxsel vs34, vs34, vs35, vs3634; CHECK-NEXT: blr35entry:36 %neg.i = xor <16 x i8> %c, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>37 %and.i = and <16 x i8> %neg.i, %a38 %and1.i = and <16 x i8> %c, %b39 %or.i = or <16 x i8> %and.i, %and1.i40 ret <16 x i8> %or.i41}42 43define dso_local <2 x i64> @test4(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {44; CHECK-LABEL: test4:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: xxsel vs34, vs34, vs35, vs3647; CHECK-NEXT: blr48entry:49 %neg.i = xor <2 x i64> %c, <i64 -1, i64 -1>50 %and.i = and <2 x i64> %a, %neg.i51 %and1.i = and <2 x i64> %c, %b52 %or.i = or <2 x i64> %and.i, %and1.i53 ret <2 x i64> %or.i54}55 56; vXi1 constants are sign-extended to preserve XXSEL pattern.57define dso_local <4 x i1> @test5(<4 x i1> %a, <4 x i1> %b, <4 x i1> %c) {58; CHECK-LABEL: test5:59; CHECK: # %bb.0: # %entry60; CHECK-NEXT: xxsel vs34, vs34, vs35, vs3661; CHECK-NEXT: blr62entry:63 %neg.i = xor <4 x i1> %c, <i1 -1, i1 -1, i1 -1, i1 -1>64 %and.i = and <4 x i1> %a, %neg.i65 %and1.i = and <4 x i1> %c, %b66 %or.i = or <4 x i1> %and.i, %and1.i67 ret <4 x i1> %or.i68}69