206 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \6; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \7; RUN: FileCheck %s --check-prefix=CHECK-BE8 9define void @test8i8(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {10; CHECK-LABEL: test8i8:11; CHECK: # %bb.0: # %entry12; CHECK-NEXT: lxvd2x vs0, 0, r413; CHECK-NEXT: xxswapd v2, vs014; CHECK-NEXT: vpkuhum v2, v2, v215; CHECK-NEXT: xxswapd vs0, v216; CHECK-NEXT: stfdx f0, 0, r317; CHECK-NEXT: blr18;19; CHECK-BE-LABEL: test8i8:20; CHECK-BE: # %bb.0: # %entry21; CHECK-BE-NEXT: lxvw4x v2, 0, r422; CHECK-BE-NEXT: addi r5, r1, -1623; CHECK-BE-NEXT: vpkuhum v2, v2, v224; CHECK-BE-NEXT: stxvd2x v2, 0, r525; CHECK-BE-NEXT: ld r4, -16(r1)26; CHECK-BE-NEXT: std r4, 0(r3)27; CHECK-BE-NEXT: blr28entry:29 %0 = load <8 x i16>, ptr %SrcPtr, align 1630 %1 = trunc <8 x i16> %0 to <8 x i8>31 store <8 x i8> %1, ptr %Sink, align 1632 ret void33}34 35define void @test4i8(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {36; CHECK-LABEL: test4i8:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: lxvd2x vs0, 0, r439; CHECK-NEXT: xxswapd v2, vs040; CHECK-NEXT: vpkuhum v2, v2, v241; CHECK-NEXT: xxsldwi vs0, v2, v2, 242; CHECK-NEXT: stfiwx f0, 0, r343; CHECK-NEXT: blr44;45; CHECK-BE-LABEL: test4i8:46; CHECK-BE: # %bb.0: # %entry47; CHECK-BE-NEXT: lxvw4x v2, 0, r448; CHECK-BE-NEXT: addi r5, r1, -1649; CHECK-BE-NEXT: vpkuhum v2, v2, v250; CHECK-BE-NEXT: stxvw4x v2, 0, r551; CHECK-BE-NEXT: lwz r4, -16(r1)52; CHECK-BE-NEXT: stw r4, 0(r3)53; CHECK-BE-NEXT: blr54entry:55 %0 = load <4 x i16>, ptr %SrcPtr, align 1656 %1 = trunc <4 x i16> %0 to <4 x i8>57 store <4 x i8> %1, ptr %Sink, align 1658 ret void59}60 61define void @test4i8w(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {62; CHECK-LABEL: test4i8w:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: lxvd2x vs0, 0, r465; CHECK-NEXT: addis r4, r2, .LCPI2_0@toc@ha66; CHECK-NEXT: addi r4, r4, .LCPI2_0@toc@l67; CHECK-NEXT: xxswapd v2, vs068; CHECK-NEXT: lxvd2x vs0, 0, r469; CHECK-NEXT: xxswapd v3, vs070; CHECK-NEXT: vperm v2, v2, v2, v371; CHECK-NEXT: xxsldwi vs0, v2, v2, 272; CHECK-NEXT: stfiwx f0, 0, r373; CHECK-NEXT: blr74;75; CHECK-BE-LABEL: test4i8w:76; CHECK-BE: # %bb.0: # %entry77; CHECK-BE-NEXT: addis r5, r2, .LCPI2_0@toc@ha78; CHECK-BE-NEXT: lxvw4x v2, 0, r479; CHECK-BE-NEXT: addi r4, r5, .LCPI2_0@toc@l80; CHECK-BE-NEXT: lxvw4x v3, 0, r481; CHECK-BE-NEXT: addi r4, r1, -1682; CHECK-BE-NEXT: vperm v2, v2, v2, v383; CHECK-BE-NEXT: stxvw4x v2, 0, r484; CHECK-BE-NEXT: lwz r4, -16(r1)85; CHECK-BE-NEXT: stw r4, 0(r3)86; CHECK-BE-NEXT: blr87entry:88 %0 = load <4 x i32>, ptr %SrcPtr, align 1689 %1 = trunc <4 x i32> %0 to <4 x i8>90 store <4 x i8> %1, ptr %Sink, align 1691 ret void92}93 94define void @test2i8(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {95; CHECK-LABEL: test2i8:96; CHECK: # %bb.0: # %entry97; CHECK-NEXT: lxvd2x vs0, 0, r498; CHECK-NEXT: xxswapd v2, vs099; CHECK-NEXT: vpkuhum v2, v2, v2100; CHECK-NEXT: xxswapd vs0, v2101; CHECK-NEXT: mffprd r4, f0102; CHECK-NEXT: clrldi r4, r4, 48103; CHECK-NEXT: sth r4, 0(r3)104; CHECK-NEXT: blr105;106; CHECK-BE-LABEL: test2i8:107; CHECK-BE: # %bb.0: # %entry108; CHECK-BE-NEXT: lxvw4x v2, 0, r4109; CHECK-BE-NEXT: addi r5, r1, -16110; CHECK-BE-NEXT: vpkuhum v2, v2, v2111; CHECK-BE-NEXT: stxvw4x v2, 0, r5112; CHECK-BE-NEXT: lhz r4, -16(r1)113; CHECK-BE-NEXT: sth r4, 0(r3)114; CHECK-BE-NEXT: blr115entry:116 %0 = load <2 x i16>, ptr %SrcPtr, align 16117 %1 = trunc <2 x i16> %0 to <2 x i8>118 store <2 x i8> %1, ptr %Sink, align 16119 ret void120}121 122define void @test4i16(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {123; CHECK-LABEL: test4i16:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: lxvd2x vs0, 0, r4126; CHECK-NEXT: xxswapd v2, vs0127; CHECK-NEXT: vpkuwum v2, v2, v2128; CHECK-NEXT: xxswapd vs0, v2129; CHECK-NEXT: stfdx f0, 0, r3130; CHECK-NEXT: blr131;132; CHECK-BE-LABEL: test4i16:133; CHECK-BE: # %bb.0: # %entry134; CHECK-BE-NEXT: lxvw4x v2, 0, r4135; CHECK-BE-NEXT: addi r5, r1, -16136; CHECK-BE-NEXT: vpkuwum v2, v2, v2137; CHECK-BE-NEXT: stxvd2x v2, 0, r5138; CHECK-BE-NEXT: ld r4, -16(r1)139; CHECK-BE-NEXT: std r4, 0(r3)140; CHECK-BE-NEXT: blr141entry:142 %0 = load <4 x i32>, ptr %SrcPtr, align 16143 %1 = trunc <4 x i32> %0 to <4 x i16>144 store <4 x i16> %1, ptr %Sink, align 16145 ret void146}147 148define void @test2i16(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {149; CHECK-LABEL: test2i16:150; CHECK: # %bb.0: # %entry151; CHECK-NEXT: lxvd2x vs0, 0, r4152; CHECK-NEXT: xxswapd v2, vs0153; CHECK-NEXT: vpkuwum v2, v2, v2154; CHECK-NEXT: xxsldwi vs0, v2, v2, 2155; CHECK-NEXT: stfiwx f0, 0, r3156; CHECK-NEXT: blr157;158; CHECK-BE-LABEL: test2i16:159; CHECK-BE: # %bb.0: # %entry160; CHECK-BE-NEXT: lxvw4x v2, 0, r4161; CHECK-BE-NEXT: addi r5, r1, -16162; CHECK-BE-NEXT: vpkuwum v2, v2, v2163; CHECK-BE-NEXT: stxvw4x v2, 0, r5164; CHECK-BE-NEXT: lwz r4, -16(r1)165; CHECK-BE-NEXT: stw r4, 0(r3)166; CHECK-BE-NEXT: blr167entry:168 %0 = load <2 x i32>, ptr %SrcPtr, align 16169 %1 = trunc <2 x i32> %0 to <2 x i16>170 store <2 x i16> %1, ptr %Sink, align 16171 ret void172}173 174define void @test2i16d(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {175; CHECK-LABEL: test2i16d:176; CHECK: # %bb.0: # %entry177; CHECK-NEXT: lxvd2x vs0, 0, r4178; CHECK-NEXT: addis r4, r2, .LCPI6_0@toc@ha179; CHECK-NEXT: addi r4, r4, .LCPI6_0@toc@l180; CHECK-NEXT: xxswapd v2, vs0181; CHECK-NEXT: lxvd2x vs0, 0, r4182; CHECK-NEXT: xxswapd v3, vs0183; CHECK-NEXT: vperm v2, v2, v2, v3184; CHECK-NEXT: xxsldwi vs0, v2, v2, 2185; CHECK-NEXT: stfiwx f0, 0, r3186; CHECK-NEXT: blr187;188; CHECK-BE-LABEL: test2i16d:189; CHECK-BE: # %bb.0: # %entry190; CHECK-BE-NEXT: addis r5, r2, .LCPI6_0@toc@ha191; CHECK-BE-NEXT: lxvw4x v2, 0, r4192; CHECK-BE-NEXT: addi r4, r5, .LCPI6_0@toc@l193; CHECK-BE-NEXT: lxvw4x v3, 0, r4194; CHECK-BE-NEXT: addi r4, r1, -16195; CHECK-BE-NEXT: vperm v2, v2, v2, v3196; CHECK-BE-NEXT: stxvw4x v2, 0, r4197; CHECK-BE-NEXT: lwz r4, -16(r1)198; CHECK-BE-NEXT: stw r4, 0(r3)199; CHECK-BE-NEXT: blr200entry:201 %0 = load <2 x i64>, ptr %SrcPtr, align 16202 %1 = trunc <2 x i64> %0 to <2 x i16>203 store <2 x i16> %1, ptr %Sink, align 16204 ret void205}206