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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s3; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s4 5; Check the vabsd* instructions that were added in PowerISA V3.06 7; Function Attrs: nounwind readnone8declare <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8>, <16 x i8>)9 10; Function Attrs: nounwind readnone11declare <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16>, <8 x i16>)12 13; Function Attrs: nounwind readnone14declare <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32>, <4 x i32>)15 16define <16 x i8> @test_byte(<16 x i8> %a, <16 x i8> %b) {17; CHECK-LABEL: test_byte:18; CHECK: # %bb.0: # %entry19; CHECK-NEXT: vabsdub 2, 2, 320; CHECK-NEXT: blr21entry:22 %res = tail call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> %a, <16 x i8> %b)23 ret <16 x i8> %res24}25 26define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) {27; CHECK-LABEL: test_half:28; CHECK: # %bb.0: # %entry29; CHECK-NEXT: vabsduh 2, 2, 330; CHECK-NEXT: blr31entry:32 %res = tail call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> %a, <8 x i16> %b)33 ret <8 x i16> %res34}35 36define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) {37; CHECK-LABEL: test_word:38; CHECK: # %bb.0: # %entry39; CHECK-NEXT: vabsduw 2, 2, 340; CHECK-NEXT: blr41entry:42 %res = tail call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> %a, <4 x i32> %b)43 ret <4 x i32> %res44}45 46define <16 x i8> @test_vabsdub(<16 x i8> %0, <16 x i8> %1) {47; CHECK-LABEL: test_vabsdub:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: vabsdub 2, 2, 350; CHECK-NEXT: blr51entry:52 %2 = zext <16 x i8> %0 to <16 x i32>53 %3 = zext <16 x i8> %1 to <16 x i32>54 %4 = sub nsw <16 x i32> %2, %355 %5 = icmp slt <16 x i32> %4, zeroinitializer56 %6 = sub nsw <16 x i32> zeroinitializer, %457 %7 = select <16 x i1> %5, <16 x i32> %6, <16 x i32> %458 %8 = trunc <16 x i32> %7 to <16 x i8>59 ret <16 x i8> %860}61 62define <8 x i16> @test_vabsduh(<8 x i16> %0, <8 x i16> %1) {63; CHECK-LABEL: test_vabsduh:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: vabsduh 2, 2, 366; CHECK-NEXT: blr67entry:68 %2 = zext <8 x i16> %0 to <8 x i32>69 %3 = zext <8 x i16> %1 to <8 x i32>70 %4 = sub nsw <8 x i32> %2, %371 %5 = icmp slt <8 x i32> %4, zeroinitializer72 %6 = sub nsw <8 x i32> zeroinitializer, %473 %7 = select <8 x i1> %5, <8 x i32> %6, <8 x i32> %474 %8 = trunc <8 x i32> %7 to <8 x i16>75 ret <8 x i16> %876}77 78define <4 x i32> @test_vabsduw(<4 x i32> %0, <4 x i32> %1) {79; CHECK-LABEL: test_vabsduw:80; CHECK: # %bb.0: # %entry81; CHECK-NEXT: xvnegsp 35, 3582; CHECK-NEXT: xvnegsp 34, 3483; CHECK-NEXT: vabsduw 2, 2, 384; CHECK-NEXT: blr85entry:86 %2 = sub nsw <4 x i32> %0, %187 %3 = icmp slt <4 x i32> %2, zeroinitializer88 %4 = sub nsw <4 x i32> zeroinitializer, %289 %5 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %290 ret <4 x i32> %591}92