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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=ALL,VSX3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefixes=ALL,NOVSX4 5; Check VMX 64-bit integer operations6 7define <2 x i64> @test_add(<2 x i64> %x, <2 x i64> %y) nounwind {8; ALL-LABEL: test_add:9; ALL: # %bb.0:10; ALL-NEXT: vaddudm 2, 2, 311; ALL-NEXT: blr12 %result = add <2 x i64> %x, %y13 ret <2 x i64> %result14}15 16define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind {17; VSX-LABEL: increment_by_one:18; VSX: # %bb.0:19; VSX-NEXT: xxleqv 35, 35, 3520; VSX-NEXT: vsubudm 2, 2, 321; VSX-NEXT: blr22;23; NOVSX-LABEL: increment_by_one:24; NOVSX: # %bb.0:25; NOVSX-NEXT: addis 3, 2, .LCPI1_0@toc@ha26; NOVSX-NEXT: addi 3, 3, .LCPI1_0@toc@l27; NOVSX-NEXT: lvx 3, 0, 328; NOVSX-NEXT: vaddudm 2, 2, 329; NOVSX-NEXT: blr30 %result = add <2 x i64> %x, <i64 1, i64 1>31 ret <2 x i64> %result32}33 34define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {35; VSX-LABEL: increment_by_val:36; VSX: # %bb.0:37; VSX-NEXT: mtfprd 0, 538; VSX-NEXT: xxspltd 35, 0, 039; VSX-NEXT: vaddudm 2, 2, 340; VSX-NEXT: blr41;42; NOVSX-LABEL: increment_by_val:43; NOVSX: # %bb.0:44; NOVSX-NEXT: addi 3, 1, -1645; NOVSX-NEXT: std 5, -8(1)46; NOVSX-NEXT: std 5, -16(1)47; NOVSX-NEXT: lvx 3, 0, 348; NOVSX-NEXT: vaddudm 2, 2, 349; NOVSX-NEXT: blr50 %tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 051 %tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 152 %result = add <2 x i64> %x, %tmpvec253 ret <2 x i64> %result54; FIXME: This is currently generating the following instruction sequence55; std 5, -8(1)56; std 5, -16(1)57; addi 3, 1, -1658; ori 2, 2, 059; lxvd2x 35, 0, 360; vaddudm 2, 2, 361; blr62; This will almost certainly cause a load-hit-store hazard.63; Since val is a value parameter, it should not need to be64; saved onto the stack at all (unless we're using this to set65; up the vector register). Instead, it would be better to splat66; the value into a vector register.67}68 69define <2 x i64> @test_sub(<2 x i64> %x, <2 x i64> %y) nounwind {70; ALL-LABEL: test_sub:71; ALL: # %bb.0:72; ALL-NEXT: vsubudm 2, 2, 373; ALL-NEXT: blr74 %result = sub <2 x i64> %x, %y75 ret <2 x i64> %result76}77 78define <2 x i64> @decrement_by_one(<2 x i64> %x) nounwind {79; VSX-LABEL: decrement_by_one:80; VSX: # %bb.0:81; VSX-NEXT: xxleqv 35, 35, 3582; VSX-NEXT: vsubudm 2, 2, 383; VSX-NEXT: blr84;85; NOVSX-LABEL: decrement_by_one:86; NOVSX: # %bb.0:87; NOVSX-NEXT: addis 3, 2, .LCPI4_0@toc@ha88; NOVSX-NEXT: addi 3, 3, .LCPI4_0@toc@l89; NOVSX-NEXT: lvx 3, 0, 390; NOVSX-NEXT: vsubudm 2, 2, 391; NOVSX-NEXT: blr92 %result = sub <2 x i64> %x, <i64 -1, i64 -1>93 ret <2 x i64> %result94}95 96define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind {97; VSX-LABEL: decrement_by_val:98; VSX: # %bb.0:99; VSX-NEXT: mtfprd 0, 5100; VSX-NEXT: xxspltd 35, 0, 0101; VSX-NEXT: vsubudm 2, 2, 3102; VSX-NEXT: blr103;104; NOVSX-LABEL: decrement_by_val:105; NOVSX: # %bb.0:106; NOVSX-NEXT: addi 3, 1, -16107; NOVSX-NEXT: std 5, -8(1)108; NOVSX-NEXT: std 5, -16(1)109; NOVSX-NEXT: lvx 3, 0, 3110; NOVSX-NEXT: vsubudm 2, 2, 3111; NOVSX-NEXT: blr112 %tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0113 %tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1114 %result = sub <2 x i64> %x, %tmpvec2115 ret <2 x i64> %result116}117