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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=ALL,VSX3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefixes=ALL,NOVSX4 5; Check VMX 128-bit integer operations6 7define <1 x i128> @out_of_bounds_insertelement(<1 x i128> %x, i128 %val) nounwind {8; ALL-LABEL: out_of_bounds_insertelement:9; ALL: # %bb.0:10; ALL-NEXT: blr11 %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 112 %result = add <1 x i128> %x, %tmpvec13 ret <1 x i128> %result14}15 16define <1 x i128> @test_add(<1 x i128> %x, <1 x i128> %y) nounwind {17; ALL-LABEL: test_add:18; ALL: # %bb.0:19; ALL-NEXT: vadduqm 2, 2, 320; ALL-NEXT: blr21 %result = add <1 x i128> %x, %y22 ret <1 x i128> %result23}24 25define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind {26; VSX-LABEL: increment_by_one:27; VSX: # %bb.0:28; VSX-NEXT: addis 3, 2, .LCPI2_0@toc@ha29; VSX-NEXT: addi 3, 3, .LCPI2_0@toc@l30; VSX-NEXT: lxvd2x 35, 0, 331; VSX-NEXT: vadduqm 2, 2, 332; VSX-NEXT: blr33;34; NOVSX-LABEL: increment_by_one:35; NOVSX: # %bb.0:36; NOVSX-NEXT: addis 3, 2, .LCPI2_0@toc@ha37; NOVSX-NEXT: addi 3, 3, .LCPI2_0@toc@l38; NOVSX-NEXT: lvx 3, 0, 339; NOVSX-NEXT: vadduqm 2, 2, 340; NOVSX-NEXT: blr41 %result = add <1 x i128> %x, <i128 1>42 ret <1 x i128> %result43}44 45define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {46; VSX-LABEL: increment_by_val:47; VSX: # %bb.0:48; VSX-NEXT: mtfprd 0, 649; VSX-NEXT: mtfprd 1, 550; VSX-NEXT: xxmrghd 35, 1, 051; VSX-NEXT: vadduqm 2, 2, 352; VSX-NEXT: blr53;54; NOVSX-LABEL: increment_by_val:55; NOVSX: # %bb.0:56; NOVSX-NEXT: addi 3, 1, -1657; NOVSX-NEXT: std 6, -8(1)58; NOVSX-NEXT: std 5, -16(1)59; NOVSX-NEXT: lvx 3, 0, 360; NOVSX-NEXT: vadduqm 2, 2, 361; NOVSX-NEXT: blr62 %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 063 %result = add <1 x i128> %x, %tmpvec64 ret <1 x i128> %result65}66 67define <1 x i128> @test_sub(<1 x i128> %x, <1 x i128> %y) nounwind {68; ALL-LABEL: test_sub:69; ALL: # %bb.0:70; ALL-NEXT: vsubuqm 2, 2, 371; ALL-NEXT: blr72 %result = sub <1 x i128> %x, %y73 ret <1 x i128> %result74}75 76define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind {77; VSX-LABEL: decrement_by_one:78; VSX: # %bb.0:79; VSX-NEXT: addis 3, 2, .LCPI5_0@toc@ha80; VSX-NEXT: addi 3, 3, .LCPI5_0@toc@l81; VSX-NEXT: lxvd2x 35, 0, 382; VSX-NEXT: vsubuqm 2, 2, 383; VSX-NEXT: blr84;85; NOVSX-LABEL: decrement_by_one:86; NOVSX: # %bb.0:87; NOVSX-NEXT: addis 3, 2, .LCPI5_0@toc@ha88; NOVSX-NEXT: addi 3, 3, .LCPI5_0@toc@l89; NOVSX-NEXT: lvx 3, 0, 390; NOVSX-NEXT: vsubuqm 2, 2, 391; NOVSX-NEXT: blr92 %result = sub <1 x i128> %x, <i128 1>93 ret <1 x i128> %result94}95 96define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {97; VSX-LABEL: decrement_by_val:98; VSX: # %bb.0:99; VSX-NEXT: mtfprd 0, 6100; VSX-NEXT: mtfprd 1, 5101; VSX-NEXT: xxmrghd 35, 1, 0102; VSX-NEXT: vsubuqm 2, 2, 3103; VSX-NEXT: blr104;105; NOVSX-LABEL: decrement_by_val:106; NOVSX: # %bb.0:107; NOVSX-NEXT: addi 3, 1, -16108; NOVSX-NEXT: std 6, -8(1)109; NOVSX-NEXT: std 5, -16(1)110; NOVSX-NEXT: lvx 3, 0, 3111; NOVSX-NEXT: vsubuqm 2, 2, 3112; NOVSX-NEXT: blr113 %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0114 %result = sub <1 x i128> %x, %tmpvec115 ret <1 x i128> %result116}117 118declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x, <1 x i128> %y, <1 x i128> %z) nounwind readnone119declare <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x, <1 x i128> %y) nounwind readnone120declare <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x, <1 x i128> %y, <1 x i128> %z) nounwind readnone121declare <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x, <1 x i128> %y, <1 x i128> %z) nounwind readnone122declare <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x, <1 x i128> %y) nounwind readnone123declare <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x, <1 x i128> %y, <1 x i128> %z) nounwind readnone124 125define <1 x i128> @test_vaddeuqm(<1 x i128> %x, <1 x i128> %y, <1 x i128> %z) nounwind {126; ALL-LABEL: test_vaddeuqm:127; ALL: # %bb.0:128; ALL-NEXT: vaddeuqm 2, 2, 3, 4129; ALL-NEXT: blr130 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,131 <1 x i128> %y,132 <1 x i128> %z)133 ret <1 x i128> %tmp134}135 136define <1 x i128> @test_vaddcuq(<1 x i128> %x, <1 x i128> %y) nounwind {137; ALL-LABEL: test_vaddcuq:138; ALL: # %bb.0:139; ALL-NEXT: vaddcuq 2, 2, 3140; ALL-NEXT: blr141 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,142 <1 x i128> %y)143 ret <1 x i128> %tmp144}145 146define <1 x i128> @test_vaddecuq(<1 x i128> %x, <1 x i128> %y, <1 x i128> %z) nounwind {147; ALL-LABEL: test_vaddecuq:148; ALL: # %bb.0:149; ALL-NEXT: vaddecuq 2, 2, 3, 4150; ALL-NEXT: blr151 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,152 <1 x i128> %y,153 <1 x i128> %z)154 ret <1 x i128> %tmp155}156 157define <1 x i128> @test_vsubeuqm(<1 x i128> %x, <1 x i128> %y, <1 x i128> %z) nounwind {158; ALL-LABEL: test_vsubeuqm:159; ALL: # %bb.0:160; ALL-NEXT: vsubeuqm 2, 2, 3, 4161; ALL-NEXT: blr162 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,163 <1 x i128> %y,164 <1 x i128> %z)165 ret <1 x i128> %tmp166}167 168define <1 x i128> @test_vsubcuq(<1 x i128> %x, <1 x i128> %y) nounwind {169; ALL-LABEL: test_vsubcuq:170; ALL: # %bb.0:171; ALL-NEXT: vsubcuq 2, 2, 3172; ALL-NEXT: blr173 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,174 <1 x i128> %y)175 ret <1 x i128> %tmp176}177 178define <1 x i128> @test_vsubecuq(<1 x i128> %x, <1 x i128> %y, <1 x i128> %z) nounwind {179; ALL-LABEL: test_vsubecuq:180; ALL: # %bb.0:181; ALL-NEXT: vsubecuq 2, 2, 3, 4182; ALL-NEXT: blr183 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,184 <1 x i128> %y,185 <1 x i128> %z)186 ret <1 x i128> %tmp187}188