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1; Test the doubleword comparison instructions that were added in POWER82;3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s5 6define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone {7 %cmp = icmp eq <2 x i64> %x, %y8 %result = sext <2 x i1> %cmp to <2 x i64>9 ret <2 x i64> %result10; CHECK-LABEL: v2si64_cmp:11; CHECK: vcmpequd 2, 2, 312}13 14define <4 x i64> @v4si64_cmp(<4 x i64> %x, <4 x i64> %y) nounwind readnone {15 %cmp = icmp eq <4 x i64> %x, %y16 %result = sext <4 x i1> %cmp to <4 x i64>17 ret <4 x i64> %result18; CHECK-LABEL: v4si64_cmp19; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}20; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}21}22 23define <8 x i64> @v8si64_cmp(<8 x i64> %x, <8 x i64> %y) nounwind readnone {24 %cmp = icmp eq <8 x i64> %x, %y25 %result = sext <8 x i1> %cmp to <8 x i64>26 ret <8 x i64> %result27; CHECK-LABEL: v8si64_cmp28; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}29; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}30; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}31; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}32}33 34define <16 x i64> @v16si64_cmp(<16 x i64> %x, <16 x i64> %y) nounwind readnone {35 %cmp = icmp eq <16 x i64> %x, %y36 %result = sext <16 x i1> %cmp to <16 x i64>37 ret <16 x i64> %result38; CHECK-LABEL: v16si64_cmp39; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}40; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}41; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}42; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}43; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}44; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}45; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}46; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}47}48 49define <32 x i64> @v32si64_cmp(<32 x i64> %x, <32 x i64> %y) nounwind readnone {50 %cmp = icmp eq <32 x i64> %x, %y51 %result = sext <32 x i1> %cmp to <32 x i64>52 ret <32 x i64> %result53; CHECK-LABEL: v32si64_cmp54; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}55; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}56; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}57; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}58; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}59; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}60; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}61; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}62; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}63; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}64; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}65; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}66; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}67; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}68; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}69; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}70}71 72; Greater than signed73define <2 x i64> @v2si64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {74 %cmp = icmp sgt <2 x i64> %x, %y75 %result = sext <2 x i1> %cmp to <2 x i64>76 ret <2 x i64> %result77; CHECK-LABEL: v2si64_cmp_gt78; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}79}80 81define <4 x i64> @v4si64_cmp_gt(<4 x i64> %x, <4 x i64> %y) nounwind readnone {82 %cmp = icmp sgt <4 x i64> %x, %y83 %result = sext <4 x i1> %cmp to <4 x i64>84 ret <4 x i64> %result85; CHECK-LABEL: v4si64_cmp_gt86; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}87; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}88}89 90define <8 x i64> @v8si64_cmp_gt(<8 x i64> %x, <8 x i64> %y) nounwind readnone {91 %cmp = icmp sgt <8 x i64> %x, %y92 %result = sext <8 x i1> %cmp to <8 x i64>93 ret <8 x i64> %result94; CHECK-LABEL: v8si64_cmp_gt95; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}96; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}97; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}98; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}99}100 101define <16 x i64> @v16si64_cmp_gt(<16 x i64> %x, <16 x i64> %y) nounwind readnone {102 %cmp = icmp sgt <16 x i64> %x, %y103 %result = sext <16 x i1> %cmp to <16 x i64>104 ret <16 x i64> %result105; CHECK-LABEL: v16si64_cmp_gt106; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}107; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}108; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}109; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}110; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}111; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}112; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}113; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}114}115 116define <32 x i64> @v32si64_cmp_gt(<32 x i64> %x, <32 x i64> %y) nounwind readnone {117 %cmp = icmp sgt <32 x i64> %x, %y118 %result = sext <32 x i1> %cmp to <32 x i64>119 ret <32 x i64> %result120; CHECK-LABEL: v32si64_cmp_gt121; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}122; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}123; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}124; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}125; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}126; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}127; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}128; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}129; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}130; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}131; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}132; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}133; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}134; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}135; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}136; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}137}138 139; Greater than unsigned140define <2 x i64> @v2ui64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {141 %cmp = icmp ugt <2 x i64> %x, %y142 %result = sext <2 x i1> %cmp to <2 x i64>143 ret <2 x i64> %result144; CHECK-LABEL: v2ui64_cmp_gt145; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}146}147 148define <4 x i64> @v4ui64_cmp_gt(<4 x i64> %x, <4 x i64> %y) nounwind readnone {149 %cmp = icmp ugt <4 x i64> %x, %y150 %result = sext <4 x i1> %cmp to <4 x i64>151 ret <4 x i64> %result152; CHECK-LABEL: v4ui64_cmp_gt153; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}154; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}155}156 157define <8 x i64> @v8ui64_cmp_gt(<8 x i64> %x, <8 x i64> %y) nounwind readnone {158 %cmp = icmp ugt <8 x i64> %x, %y159 %result = sext <8 x i1> %cmp to <8 x i64>160 ret <8 x i64> %result161; CHECK-LABEL: v8ui64_cmp_gt162; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}163; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}164; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}165; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}166}167 168define <16 x i64> @v16ui64_cmp_gt(<16 x i64> %x, <16 x i64> %y) nounwind readnone {169 %cmp = icmp ugt <16 x i64> %x, %y170 %result = sext <16 x i1> %cmp to <16 x i64>171 ret <16 x i64> %result172; CHECK-LABEL: v16ui64_cmp_gt173; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}174; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}175; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}176; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}177; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}178; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}179; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}180; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}181}182 183define <32 x i64> @v32ui64_cmp_gt(<32 x i64> %x, <32 x i64> %y) nounwind readnone {184 %cmp = icmp ugt <32 x i64> %x, %y185 %result = sext <32 x i1> %cmp to <32 x i64>186 ret <32 x i64> %result187; CHECK-LABEL: v32ui64_cmp_gt188; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}189; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}190; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}191; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}192; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}193; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}194; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}195; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}196; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}197; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}198; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}199; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}200; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}201; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}202; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}203; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}204}205 206; Check the intrinsics also207declare <2 x i64> @llvm.ppc.altivec.vcmpequd(<2 x i64>, <2 x i64>) nounwind readnone208declare i32 @llvm.ppc.altivec.vcmpequd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone209declare <2 x i64> @llvm.ppc.altivec.vcmpgtsd(<2 x i64>, <2 x i64>) nounwind readnone210declare i32 @llvm.ppc.altivec.vcmpgtsd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone211declare <2 x i64> @llvm.ppc.altivec.vcmpgtud(<2 x i64>, <2 x i64>) nounwind readnone212declare i32 @llvm.ppc.altivec.vcmpgtud.p(i32, <2 x i64>, <2 x i64>) nounwind readnone213 214define <2 x i64> @test_vcmpequd(<2 x i64> %x, <2 x i64> %y) {215 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vcmpequd(<2 x i64> %x, <2 x i64> %y)216 ret <2 x i64> %tmp217; CHECK-LABEL: test_vcmpequd:218; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}219}220 221define i32 @test_vcmpequd_p(<2 x i64> %x, <2 x i64> %y) {222 %tmp = tail call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> %x, <2 x i64> %y)223 ret i32 %tmp224; CHECK-LABEL: test_vcmpequd_p:225; CHECK: vcmpequd. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}226}227 228define <2 x i64> @test_vcmpgtsd(<2 x i64> %x, <2 x i64> %y) {229 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vcmpgtsd(<2 x i64> %x, <2 x i64> %y)230 ret <2 x i64> %tmp231; CHECK-LABEL: test_vcmpgtsd232; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}233}234 235define i32 @test_vcmpgtsd_p(<2 x i64> %x, <2 x i64> %y) {236 %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtsd.p(i32 2, <2 x i64> %x, <2 x i64> %y)237 ret i32 %tmp238; CHECK-LABEL: test_vcmpgtsd_p239; CHECK: vcmpgtsd. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}240}241 242define <2 x i64> @test_vcmpgtud(<2 x i64> %x, <2 x i64> %y) {243 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vcmpgtud(<2 x i64> %x, <2 x i64> %y)244 ret <2 x i64> %tmp245; CHECK-LABEL: test_vcmpgtud246; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}247}248 249define i32 @test_vcmpgtud_p(<2 x i64> %x, <2 x i64> %y) {250 %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtud.p(i32 2, <2 x i64> %x, <2 x i64> %y)251 ret i32 %tmp252; CHECK-LABEL: test_vcmpgtud_p253; CHECK: vcmpgtud. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}254}255 256 257 258 259