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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,BE3; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s --check-prefixes=CHECK,BE4; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,LE5 6; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -use-constant-int-for-fixed-length-splat -use-constant-fp-for-fixed-length-splat < %s | FileCheck %s --check-prefixes=CHECK,BE7; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -use-constant-int-for-fixed-length-splat -use-constant-fp-for-fixed-length-splat < %s | FileCheck %s --check-prefixes=CHECK,BE8; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu -use-constant-int-for-fixed-length-splat -use-constant-fp-for-fixed-length-splat < %s | FileCheck %s --check-prefixes=CHECK,LE9 10define void @test1(ptr %P1, ptr %P2, ptr %P3) nounwind {11; BE-LABEL: test1:12; BE: # %bb.0:13; BE-NEXT: lxvw4x 0, 0, 314; BE-NEXT: vspltisb 2, -115; BE-NEXT: vslw 2, 2, 216; BE-NEXT: xxland 0, 0, 3417; BE-NEXT: stxvw4x 0, 0, 318; BE-NEXT: lxvw4x 0, 0, 419; BE-NEXT: xxlandc 0, 0, 3420; BE-NEXT: stxvw4x 0, 0, 421; BE-NEXT: lxvw4x 0, 0, 522; BE-NEXT: xvabssp 0, 023; BE-NEXT: stxvw4x 0, 0, 524; BE-NEXT: blr25;26; LE-LABEL: test1:27; LE: # %bb.0:28; LE-NEXT: lxvd2x 0, 0, 329; LE-NEXT: xxswapd 34, 030; LE-NEXT: vspltisb 3, -131; LE-NEXT: vslw 3, 3, 332; LE-NEXT: xxland 0, 34, 3533; LE-NEXT: xxswapd 0, 034; LE-NEXT: stxvd2x 0, 0, 335; LE-NEXT: lxvd2x 0, 0, 436; LE-NEXT: xxswapd 34, 037; LE-NEXT: xxlandc 0, 34, 3538; LE-NEXT: xxswapd 0, 039; LE-NEXT: stxvd2x 0, 0, 440; LE-NEXT: lxvd2x 0, 0, 541; LE-NEXT: xxswapd 34, 042; LE-NEXT: xvabssp 0, 3443; LE-NEXT: xxswapd 0, 044; LE-NEXT: stxvd2x 0, 0, 545; LE-NEXT: blr46 %tmp = load <4 x i32>, ptr %P1 ; <<4 x i32>> [#uses=1]47 %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]48 store <4 x i32> %tmp4, ptr %P149 %tmp7 = load <4 x i32>, ptr %P2 ; <<4 x i32>> [#uses=1]50 %tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]51 store <4 x i32> %tmp9, ptr %P252 %tmp.upgrd.1 = load <4 x float>, ptr %P3 ; <<4 x float>> [#uses=1]53 %tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1]54 %tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]55 %tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1]56 store <4 x float> %tmp13, ptr %P357 ret void58 59}60 61define <4 x i32> @test_30() nounwind {62; CHECK-LABEL: test_30:63; CHECK: # %bb.0:64; CHECK-NEXT: vspltisw 2, 1565; CHECK-NEXT: vadduwm 2, 2, 266; CHECK-NEXT: blr67 ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >68}69 70define <4 x i32> @test_29() nounwind {71; CHECK-LABEL: test_29:72; CHECK: # %bb.0:73; CHECK-NEXT: vspltisw 3, -1674; CHECK-NEXT: vspltisw 2, 1375; CHECK-NEXT: vsubuwm 2, 2, 376; CHECK-NEXT: blr77 ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >78}79 80define <8 x i16> @test_n30() nounwind {81; CHECK-LABEL: test_n30:82; CHECK: # %bb.0:83; CHECK-NEXT: vspltish 2, -1584; CHECK-NEXT: vadduhm 2, 2, 285; CHECK-NEXT: blr86 ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >87}88 89define <16 x i8> @test_n104() nounwind {90; CHECK-LABEL: test_n104:91; CHECK: # %bb.0:92; CHECK-NEXT: vspltisb 2, -1393; CHECK-NEXT: vslb 2, 2, 294; CHECK-NEXT: blr95 ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >96}97 98define <4 x i32> @test_vsldoi() nounwind {99; CHECK-LABEL: test_vsldoi:100; CHECK: # %bb.0:101; CHECK-NEXT: vspltisw 2, 2102; CHECK-NEXT: vsldoi 2, 2, 2, 1103; CHECK-NEXT: blr104 ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >105}106 107define <8 x i16> @test_vsldoi_65023() nounwind {108; CHECK-LABEL: test_vsldoi_65023:109; CHECK: # %bb.0:110; CHECK-NEXT: vspltish 2, -3111; CHECK-NEXT: vsldoi 2, 2, 2, 1112; CHECK-NEXT: blr113 ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >114}115 116define <4 x i32> @test_vsldoi_x16() nounwind {117; CHECK-LABEL: test_vsldoi_x16:118; CHECK: # %bb.0:119; CHECK-NEXT: vspltisw 2, -3120; CHECK-NEXT: vsldoi 2, 2, 2, 2121; CHECK-NEXT: blr122 ret <4 x i32> <i32 -131073, i32 -131073, i32 -131073, i32 -131073>123}124 125define <4 x i32> @test_vsldoi_x24() nounwind {126; CHECK-LABEL: test_vsldoi_x24:127; CHECK: # %bb.0:128; CHECK-NEXT: vspltisw 2, -3129; CHECK-NEXT: vsldoi 2, 2, 2, 3130; CHECK-NEXT: blr131 ret <4 x i32> <i32 -33554433, i32 -33554433, i32 -33554433, i32 -33554433>132}133 134define <4 x i32> @test_rol() nounwind {135; CHECK-LABEL: test_rol:136; CHECK: # %bb.0:137; CHECK-NEXT: vspltisw 2, -12138; CHECK-NEXT: vrlw 2, 2, 2139; CHECK-NEXT: blr140 ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >141}142