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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s --check-prefix=CHECK-P85; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \7; RUN: FileCheck %s --check-prefix=CHECK-P98; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \9; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \10; RUN: FileCheck %s --check-prefix=CHECK-BE11 12define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {13; CHECK-P8-LABEL: test2elt:14; CHECK-P8: # %bb.0: # %entry15; CHECK-P8-NEXT: mtfprd f0, r316; CHECK-P8-NEXT: xxswapd v2, vs017; CHECK-P8-NEXT: xxmrglw vs0, v2, v218; CHECK-P8-NEXT: xvcvspdp vs0, vs019; CHECK-P8-NEXT: xvcvdpuxds v2, vs020; CHECK-P8-NEXT: blr21;22; CHECK-P9-LABEL: test2elt:23; CHECK-P9: # %bb.0: # %entry24; CHECK-P9-NEXT: mtfprd f0, r325; CHECK-P9-NEXT: xxswapd v2, vs026; CHECK-P9-NEXT: xxmrglw vs0, v2, v227; CHECK-P9-NEXT: xvcvspdp vs0, vs028; CHECK-P9-NEXT: xvcvdpuxds v2, vs029; CHECK-P9-NEXT: blr30;31; CHECK-BE-LABEL: test2elt:32; CHECK-BE: # %bb.0: # %entry33; CHECK-BE-NEXT: mtfprd f0, r334; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs035; CHECK-BE-NEXT: xvcvspdp vs0, vs036; CHECK-BE-NEXT: xvcvdpuxds v2, vs037; CHECK-BE-NEXT: blr38entry:39 %0 = bitcast i64 %a.coerce to <2 x float>40 %1 = fptoui <2 x float> %0 to <2 x i64>41 ret <2 x i64> %142}43 44define void @test4elt(ptr noalias nocapture sret(<4 x i64>) %agg.result, <4 x float> %a) local_unnamed_addr #1 {45; CHECK-P8-LABEL: test4elt:46; CHECK-P8: # %bb.0: # %entry47; CHECK-P8-NEXT: xxmrglw vs0, v2, v248; CHECK-P8-NEXT: xxmrghw vs1, v2, v249; CHECK-P8-NEXT: li r4, 1650; CHECK-P8-NEXT: xvcvspdp vs0, vs051; CHECK-P8-NEXT: xvcvdpuxds v2, vs052; CHECK-P8-NEXT: xvcvspdp vs0, vs153; CHECK-P8-NEXT: xvcvdpuxds v3, vs054; CHECK-P8-NEXT: xxswapd vs1, v255; CHECK-P8-NEXT: stxvd2x vs1, 0, r356; CHECK-P8-NEXT: xxswapd vs0, v357; CHECK-P8-NEXT: stxvd2x vs0, r3, r458; CHECK-P8-NEXT: blr59;60; CHECK-P9-LABEL: test4elt:61; CHECK-P9: # %bb.0: # %entry62; CHECK-P9-NEXT: xxmrglw vs0, v2, v263; CHECK-P9-NEXT: xxmrghw vs1, v2, v264; CHECK-P9-NEXT: xvcvspdp vs0, vs065; CHECK-P9-NEXT: xvcvspdp vs1, vs166; CHECK-P9-NEXT: xvcvdpuxds vs0, vs067; CHECK-P9-NEXT: xvcvdpuxds vs1, vs168; CHECK-P9-NEXT: stxv vs1, 16(r3)69; CHECK-P9-NEXT: stxv vs0, 0(r3)70; CHECK-P9-NEXT: blr71;72; CHECK-BE-LABEL: test4elt:73; CHECK-BE: # %bb.0: # %entry74; CHECK-BE-NEXT: xxmrghw vs0, v2, v275; CHECK-BE-NEXT: xxmrglw vs1, v2, v276; CHECK-BE-NEXT: xvcvspdp vs0, vs077; CHECK-BE-NEXT: xvcvspdp vs1, vs178; CHECK-BE-NEXT: xvcvdpuxds vs0, vs079; CHECK-BE-NEXT: xvcvdpuxds vs1, vs180; CHECK-BE-NEXT: stxv vs1, 16(r3)81; CHECK-BE-NEXT: stxv vs0, 0(r3)82; CHECK-BE-NEXT: blr83entry:84 %0 = fptoui <4 x float> %a to <4 x i64>85 store <4 x i64> %0, ptr %agg.result, align 3286 ret void87}88 89define void @test8elt(ptr noalias nocapture sret(<8 x i64>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {90; CHECK-P8-LABEL: test8elt:91; CHECK-P8: # %bb.0: # %entry92; CHECK-P8-NEXT: li r5, 1693; CHECK-P8-NEXT: lxvd2x vs0, r4, r594; CHECK-P8-NEXT: xxswapd v2, vs095; CHECK-P8-NEXT: lxvd2x vs0, 0, r496; CHECK-P8-NEXT: li r4, 4897; CHECK-P8-NEXT: xxmrglw vs1, v2, v298; CHECK-P8-NEXT: xvcvspdp vs1, vs199; CHECK-P8-NEXT: xxswapd v3, vs0100; CHECK-P8-NEXT: xxmrghw vs0, v2, v2101; CHECK-P8-NEXT: xvcvspdp vs0, vs0102; CHECK-P8-NEXT: xvcvdpuxds v2, vs1103; CHECK-P8-NEXT: xxmrglw vs2, v3, v3104; CHECK-P8-NEXT: xxmrghw vs3, v3, v3105; CHECK-P8-NEXT: xvcvspdp vs2, vs2106; CHECK-P8-NEXT: xvcvspdp vs3, vs3107; CHECK-P8-NEXT: xvcvdpuxds v3, vs0108; CHECK-P8-NEXT: xvcvdpuxds v4, vs2109; CHECK-P8-NEXT: xxswapd vs1, v2110; CHECK-P8-NEXT: xxswapd vs0, v3111; CHECK-P8-NEXT: xvcvdpuxds v3, vs3112; CHECK-P8-NEXT: stxvd2x vs0, r3, r4113; CHECK-P8-NEXT: li r4, 32114; CHECK-P8-NEXT: stxvd2x vs1, r3, r4115; CHECK-P8-NEXT: xxswapd vs3, v4116; CHECK-P8-NEXT: stxvd2x vs3, 0, r3117; CHECK-P8-NEXT: xxswapd vs2, v3118; CHECK-P8-NEXT: stxvd2x vs2, r3, r5119; CHECK-P8-NEXT: blr120;121; CHECK-P9-LABEL: test8elt:122; CHECK-P9: # %bb.0: # %entry123; CHECK-P9-NEXT: lxv vs0, 16(r4)124; CHECK-P9-NEXT: lxv vs1, 0(r4)125; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1126; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1127; CHECK-P9-NEXT: xxmrglw vs3, vs0, vs0128; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0129; CHECK-P9-NEXT: xvcvspdp vs2, vs2130; CHECK-P9-NEXT: xvcvspdp vs1, vs1131; CHECK-P9-NEXT: xvcvspdp vs3, vs3132; CHECK-P9-NEXT: xvcvspdp vs0, vs0133; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2134; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1135; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3136; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0137; CHECK-P9-NEXT: stxv vs0, 48(r3)138; CHECK-P9-NEXT: stxv vs3, 32(r3)139; CHECK-P9-NEXT: stxv vs1, 16(r3)140; CHECK-P9-NEXT: stxv vs2, 0(r3)141; CHECK-P9-NEXT: blr142;143; CHECK-BE-LABEL: test8elt:144; CHECK-BE: # %bb.0: # %entry145; CHECK-BE-NEXT: lxv vs0, 16(r4)146; CHECK-BE-NEXT: lxv vs1, 0(r4)147; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1148; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1149; CHECK-BE-NEXT: xxmrghw vs3, vs0, vs0150; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0151; CHECK-BE-NEXT: xvcvspdp vs2, vs2152; CHECK-BE-NEXT: xvcvspdp vs1, vs1153; CHECK-BE-NEXT: xvcvspdp vs3, vs3154; CHECK-BE-NEXT: xvcvspdp vs0, vs0155; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2156; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1157; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3158; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0159; CHECK-BE-NEXT: stxv vs0, 48(r3)160; CHECK-BE-NEXT: stxv vs3, 32(r3)161; CHECK-BE-NEXT: stxv vs1, 16(r3)162; CHECK-BE-NEXT: stxv vs2, 0(r3)163; CHECK-BE-NEXT: blr164entry:165 %a = load <8 x float>, ptr %0, align 32166 %1 = fptoui <8 x float> %a to <8 x i64>167 store <8 x i64> %1, ptr %agg.result, align 64168 ret void169}170 171define void @test16elt(ptr noalias nocapture sret(<16 x i64>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {172; CHECK-P8-LABEL: test16elt:173; CHECK-P8: # %bb.0: # %entry174; CHECK-P8-NEXT: li r5, 48175; CHECK-P8-NEXT: li r6, 32176; CHECK-P8-NEXT: li r7, 16177; CHECK-P8-NEXT: lxvd2x vs3, 0, r4178; CHECK-P8-NEXT: lxvd2x vs0, r4, r5179; CHECK-P8-NEXT: lxvd2x vs1, r4, r6180; CHECK-P8-NEXT: lxvd2x vs2, r4, r7181; CHECK-P8-NEXT: li r4, 112182; CHECK-P8-NEXT: xxswapd v4, vs3183; CHECK-P8-NEXT: xxswapd v2, vs0184; CHECK-P8-NEXT: xxswapd v3, vs1185; CHECK-P8-NEXT: xxmrglw vs6, v4, v4186; CHECK-P8-NEXT: xxmrghw vs7, v4, v4187; CHECK-P8-NEXT: xvcvspdp vs6, vs6188; CHECK-P8-NEXT: xvcvspdp vs7, vs7189; CHECK-P8-NEXT: xvcvdpuxds v1, vs7190; CHECK-P8-NEXT: xxmrghw vs0, v2, v2191; CHECK-P8-NEXT: xxmrglw vs1, v2, v2192; CHECK-P8-NEXT: xvcvspdp vs1, vs1193; CHECK-P8-NEXT: xvcvspdp vs0, vs0194; CHECK-P8-NEXT: xxswapd v2, vs2195; CHECK-P8-NEXT: xxmrghw vs3, v3, v3196; CHECK-P8-NEXT: xxmrglw vs2, v3, v3197; CHECK-P8-NEXT: xvcvspdp vs3, vs3198; CHECK-P8-NEXT: xvcvspdp vs2, vs2199; CHECK-P8-NEXT: xvcvdpuxds v4, vs0200; CHECK-P8-NEXT: xvcvdpuxds v0, vs1201; CHECK-P8-NEXT: xvcvdpuxds v5, vs3202; CHECK-P8-NEXT: xxmrglw vs4, v2, v2203; CHECK-P8-NEXT: xxmrghw vs5, v2, v2204; CHECK-P8-NEXT: xvcvspdp vs4, vs4205; CHECK-P8-NEXT: xvcvspdp vs5, vs5206; CHECK-P8-NEXT: xvcvdpuxds v2, vs4207; CHECK-P8-NEXT: xvcvdpuxds v3, vs5208; CHECK-P8-NEXT: xxswapd vs4, v1209; CHECK-P8-NEXT: stxvd2x vs4, r3, r7210; CHECK-P8-NEXT: xxswapd vs0, v4211; CHECK-P8-NEXT: xvcvdpuxds v4, vs2212; CHECK-P8-NEXT: xxswapd vs1, v0213; CHECK-P8-NEXT: xvcvdpuxds v0, vs6214; CHECK-P8-NEXT: stxvd2x vs0, r3, r4215; CHECK-P8-NEXT: li r4, 96216; CHECK-P8-NEXT: stxvd2x vs1, r3, r4217; CHECK-P8-NEXT: li r4, 80218; CHECK-P8-NEXT: xxswapd vs0, v5219; CHECK-P8-NEXT: stxvd2x vs0, r3, r4220; CHECK-P8-NEXT: li r4, 64221; CHECK-P8-NEXT: xxswapd vs3, v2222; CHECK-P8-NEXT: stxvd2x vs3, r3, r6223; CHECK-P8-NEXT: xxswapd vs1, v3224; CHECK-P8-NEXT: stxvd2x vs1, r3, r5225; CHECK-P8-NEXT: xxswapd vs2, v4226; CHECK-P8-NEXT: xxswapd vs5, v0227; CHECK-P8-NEXT: stxvd2x vs2, r3, r4228; CHECK-P8-NEXT: stxvd2x vs5, 0, r3229; CHECK-P8-NEXT: blr230;231; CHECK-P9-LABEL: test16elt:232; CHECK-P9: # %bb.0: # %entry233; CHECK-P9-NEXT: lxv vs0, 48(r4)234; CHECK-P9-NEXT: lxv vs1, 0(r4)235; CHECK-P9-NEXT: lxv vs3, 16(r4)236; CHECK-P9-NEXT: lxv vs5, 32(r4)237; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1238; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1239; CHECK-P9-NEXT: xxmrglw vs4, vs3, vs3240; CHECK-P9-NEXT: xxmrghw vs3, vs3, vs3241; CHECK-P9-NEXT: xxmrglw vs6, vs5, vs5242; CHECK-P9-NEXT: xxmrghw vs5, vs5, vs5243; CHECK-P9-NEXT: xxmrglw vs7, vs0, vs0244; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0245; CHECK-P9-NEXT: xvcvspdp vs2, vs2246; CHECK-P9-NEXT: xvcvspdp vs1, vs1247; CHECK-P9-NEXT: xvcvspdp vs4, vs4248; CHECK-P9-NEXT: xvcvspdp vs3, vs3249; CHECK-P9-NEXT: xvcvspdp vs6, vs6250; CHECK-P9-NEXT: xvcvspdp vs5, vs5251; CHECK-P9-NEXT: xvcvspdp vs7, vs7252; CHECK-P9-NEXT: xvcvspdp vs0, vs0253; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2254; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1255; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4256; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3257; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6258; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5259; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7260; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0261; CHECK-P9-NEXT: stxv vs0, 112(r3)262; CHECK-P9-NEXT: stxv vs7, 96(r3)263; CHECK-P9-NEXT: stxv vs5, 80(r3)264; CHECK-P9-NEXT: stxv vs6, 64(r3)265; CHECK-P9-NEXT: stxv vs3, 48(r3)266; CHECK-P9-NEXT: stxv vs4, 32(r3)267; CHECK-P9-NEXT: stxv vs1, 16(r3)268; CHECK-P9-NEXT: stxv vs2, 0(r3)269; CHECK-P9-NEXT: blr270;271; CHECK-BE-LABEL: test16elt:272; CHECK-BE: # %bb.0: # %entry273; CHECK-BE-NEXT: lxv vs0, 48(r4)274; CHECK-BE-NEXT: lxv vs1, 0(r4)275; CHECK-BE-NEXT: lxv vs3, 16(r4)276; CHECK-BE-NEXT: lxv vs5, 32(r4)277; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1278; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1279; CHECK-BE-NEXT: xxmrghw vs4, vs3, vs3280; CHECK-BE-NEXT: xxmrglw vs3, vs3, vs3281; CHECK-BE-NEXT: xxmrghw vs6, vs5, vs5282; CHECK-BE-NEXT: xxmrglw vs5, vs5, vs5283; CHECK-BE-NEXT: xxmrghw vs7, vs0, vs0284; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0285; CHECK-BE-NEXT: xvcvspdp vs2, vs2286; CHECK-BE-NEXT: xvcvspdp vs1, vs1287; CHECK-BE-NEXT: xvcvspdp vs4, vs4288; CHECK-BE-NEXT: xvcvspdp vs3, vs3289; CHECK-BE-NEXT: xvcvspdp vs6, vs6290; CHECK-BE-NEXT: xvcvspdp vs5, vs5291; CHECK-BE-NEXT: xvcvspdp vs7, vs7292; CHECK-BE-NEXT: xvcvspdp vs0, vs0293; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2294; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1295; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4296; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3297; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6298; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5299; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7300; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0301; CHECK-BE-NEXT: stxv vs0, 112(r3)302; CHECK-BE-NEXT: stxv vs7, 96(r3)303; CHECK-BE-NEXT: stxv vs5, 80(r3)304; CHECK-BE-NEXT: stxv vs6, 64(r3)305; CHECK-BE-NEXT: stxv vs3, 48(r3)306; CHECK-BE-NEXT: stxv vs4, 32(r3)307; CHECK-BE-NEXT: stxv vs1, 16(r3)308; CHECK-BE-NEXT: stxv vs2, 0(r3)309; CHECK-BE-NEXT: blr310entry:311 %a = load <16 x float>, ptr %0, align 64312 %1 = fptoui <16 x float> %a to <16 x i64>313 store <16 x i64> %1, ptr %agg.result, align 128314 ret void315}316 317define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {318; CHECK-P8-LABEL: test2elt_signed:319; CHECK-P8: # %bb.0: # %entry320; CHECK-P8-NEXT: mtfprd f0, r3321; CHECK-P8-NEXT: xxswapd v2, vs0322; CHECK-P8-NEXT: xxmrglw vs0, v2, v2323; CHECK-P8-NEXT: xvcvspdp vs0, vs0324; CHECK-P8-NEXT: xvcvdpuxds v2, vs0325; CHECK-P8-NEXT: blr326;327; CHECK-P9-LABEL: test2elt_signed:328; CHECK-P9: # %bb.0: # %entry329; CHECK-P9-NEXT: mtfprd f0, r3330; CHECK-P9-NEXT: xxswapd v2, vs0331; CHECK-P9-NEXT: xxmrglw vs0, v2, v2332; CHECK-P9-NEXT: xvcvspdp vs0, vs0333; CHECK-P9-NEXT: xvcvdpuxds v2, vs0334; CHECK-P9-NEXT: blr335;336; CHECK-BE-LABEL: test2elt_signed:337; CHECK-BE: # %bb.0: # %entry338; CHECK-BE-NEXT: mtfprd f0, r3339; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0340; CHECK-BE-NEXT: xvcvspdp vs0, vs0341; CHECK-BE-NEXT: xvcvdpuxds v2, vs0342; CHECK-BE-NEXT: blr343entry:344 %0 = bitcast i64 %a.coerce to <2 x float>345 %1 = fptoui <2 x float> %0 to <2 x i64>346 ret <2 x i64> %1347}348 349define void @test4elt_signed(ptr noalias nocapture sret(<4 x i64>) %agg.result, <4 x float> %a) local_unnamed_addr #1 {350; CHECK-P8-LABEL: test4elt_signed:351; CHECK-P8: # %bb.0: # %entry352; CHECK-P8-NEXT: xxmrglw vs0, v2, v2353; CHECK-P8-NEXT: xxmrghw vs1, v2, v2354; CHECK-P8-NEXT: li r4, 16355; CHECK-P8-NEXT: xvcvspdp vs0, vs0356; CHECK-P8-NEXT: xvcvdpuxds v2, vs0357; CHECK-P8-NEXT: xvcvspdp vs0, vs1358; CHECK-P8-NEXT: xvcvdpuxds v3, vs0359; CHECK-P8-NEXT: xxswapd vs1, v2360; CHECK-P8-NEXT: stxvd2x vs1, 0, r3361; CHECK-P8-NEXT: xxswapd vs0, v3362; CHECK-P8-NEXT: stxvd2x vs0, r3, r4363; CHECK-P8-NEXT: blr364;365; CHECK-P9-LABEL: test4elt_signed:366; CHECK-P9: # %bb.0: # %entry367; CHECK-P9-NEXT: xxmrglw vs0, v2, v2368; CHECK-P9-NEXT: xxmrghw vs1, v2, v2369; CHECK-P9-NEXT: xvcvspdp vs0, vs0370; CHECK-P9-NEXT: xvcvspdp vs1, vs1371; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0372; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1373; CHECK-P9-NEXT: stxv vs1, 16(r3)374; CHECK-P9-NEXT: stxv vs0, 0(r3)375; CHECK-P9-NEXT: blr376;377; CHECK-BE-LABEL: test4elt_signed:378; CHECK-BE: # %bb.0: # %entry379; CHECK-BE-NEXT: xxmrghw vs0, v2, v2380; CHECK-BE-NEXT: xxmrglw vs1, v2, v2381; CHECK-BE-NEXT: xvcvspdp vs0, vs0382; CHECK-BE-NEXT: xvcvspdp vs1, vs1383; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0384; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1385; CHECK-BE-NEXT: stxv vs1, 16(r3)386; CHECK-BE-NEXT: stxv vs0, 0(r3)387; CHECK-BE-NEXT: blr388entry:389 %0 = fptoui <4 x float> %a to <4 x i64>390 store <4 x i64> %0, ptr %agg.result, align 32391 ret void392}393 394define void @test8elt_signed(ptr noalias nocapture sret(<8 x i64>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {395; CHECK-P8-LABEL: test8elt_signed:396; CHECK-P8: # %bb.0: # %entry397; CHECK-P8-NEXT: li r5, 16398; CHECK-P8-NEXT: lxvd2x vs0, r4, r5399; CHECK-P8-NEXT: xxswapd v2, vs0400; CHECK-P8-NEXT: lxvd2x vs0, 0, r4401; CHECK-P8-NEXT: li r4, 48402; CHECK-P8-NEXT: xxmrglw vs1, v2, v2403; CHECK-P8-NEXT: xvcvspdp vs1, vs1404; CHECK-P8-NEXT: xxswapd v3, vs0405; CHECK-P8-NEXT: xxmrghw vs0, v2, v2406; CHECK-P8-NEXT: xvcvspdp vs0, vs0407; CHECK-P8-NEXT: xvcvdpuxds v2, vs1408; CHECK-P8-NEXT: xxmrglw vs2, v3, v3409; CHECK-P8-NEXT: xxmrghw vs3, v3, v3410; CHECK-P8-NEXT: xvcvspdp vs2, vs2411; CHECK-P8-NEXT: xvcvspdp vs3, vs3412; CHECK-P8-NEXT: xvcvdpuxds v3, vs0413; CHECK-P8-NEXT: xvcvdpuxds v4, vs2414; CHECK-P8-NEXT: xxswapd vs1, v2415; CHECK-P8-NEXT: xxswapd vs0, v3416; CHECK-P8-NEXT: xvcvdpuxds v3, vs3417; CHECK-P8-NEXT: stxvd2x vs0, r3, r4418; CHECK-P8-NEXT: li r4, 32419; CHECK-P8-NEXT: stxvd2x vs1, r3, r4420; CHECK-P8-NEXT: xxswapd vs3, v4421; CHECK-P8-NEXT: stxvd2x vs3, 0, r3422; CHECK-P8-NEXT: xxswapd vs2, v3423; CHECK-P8-NEXT: stxvd2x vs2, r3, r5424; CHECK-P8-NEXT: blr425;426; CHECK-P9-LABEL: test8elt_signed:427; CHECK-P9: # %bb.0: # %entry428; CHECK-P9-NEXT: lxv vs0, 16(r4)429; CHECK-P9-NEXT: lxv vs1, 0(r4)430; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1431; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1432; CHECK-P9-NEXT: xxmrglw vs3, vs0, vs0433; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0434; CHECK-P9-NEXT: xvcvspdp vs2, vs2435; CHECK-P9-NEXT: xvcvspdp vs1, vs1436; CHECK-P9-NEXT: xvcvspdp vs3, vs3437; CHECK-P9-NEXT: xvcvspdp vs0, vs0438; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2439; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1440; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3441; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0442; CHECK-P9-NEXT: stxv vs0, 48(r3)443; CHECK-P9-NEXT: stxv vs3, 32(r3)444; CHECK-P9-NEXT: stxv vs1, 16(r3)445; CHECK-P9-NEXT: stxv vs2, 0(r3)446; CHECK-P9-NEXT: blr447;448; CHECK-BE-LABEL: test8elt_signed:449; CHECK-BE: # %bb.0: # %entry450; CHECK-BE-NEXT: lxv vs0, 16(r4)451; CHECK-BE-NEXT: lxv vs1, 0(r4)452; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1453; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1454; CHECK-BE-NEXT: xxmrghw vs3, vs0, vs0455; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0456; CHECK-BE-NEXT: xvcvspdp vs2, vs2457; CHECK-BE-NEXT: xvcvspdp vs1, vs1458; CHECK-BE-NEXT: xvcvspdp vs3, vs3459; CHECK-BE-NEXT: xvcvspdp vs0, vs0460; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2461; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1462; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3463; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0464; CHECK-BE-NEXT: stxv vs0, 48(r3)465; CHECK-BE-NEXT: stxv vs3, 32(r3)466; CHECK-BE-NEXT: stxv vs1, 16(r3)467; CHECK-BE-NEXT: stxv vs2, 0(r3)468; CHECK-BE-NEXT: blr469entry:470 %a = load <8 x float>, ptr %0, align 32471 %1 = fptoui <8 x float> %a to <8 x i64>472 store <8 x i64> %1, ptr %agg.result, align 64473 ret void474}475 476define void @test16elt_signed(ptr noalias nocapture sret(<16 x i64>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {477; CHECK-P8-LABEL: test16elt_signed:478; CHECK-P8: # %bb.0: # %entry479; CHECK-P8-NEXT: li r5, 48480; CHECK-P8-NEXT: li r6, 32481; CHECK-P8-NEXT: li r7, 16482; CHECK-P8-NEXT: lxvd2x vs3, 0, r4483; CHECK-P8-NEXT: lxvd2x vs0, r4, r5484; CHECK-P8-NEXT: lxvd2x vs1, r4, r6485; CHECK-P8-NEXT: lxvd2x vs2, r4, r7486; CHECK-P8-NEXT: li r4, 112487; CHECK-P8-NEXT: xxswapd v4, vs3488; CHECK-P8-NEXT: xxswapd v2, vs0489; CHECK-P8-NEXT: xxswapd v3, vs1490; CHECK-P8-NEXT: xxmrglw vs6, v4, v4491; CHECK-P8-NEXT: xxmrghw vs7, v4, v4492; CHECK-P8-NEXT: xvcvspdp vs6, vs6493; CHECK-P8-NEXT: xvcvspdp vs7, vs7494; CHECK-P8-NEXT: xvcvdpuxds v1, vs7495; CHECK-P8-NEXT: xxmrghw vs0, v2, v2496; CHECK-P8-NEXT: xxmrglw vs1, v2, v2497; CHECK-P8-NEXT: xvcvspdp vs1, vs1498; CHECK-P8-NEXT: xvcvspdp vs0, vs0499; CHECK-P8-NEXT: xxswapd v2, vs2500; CHECK-P8-NEXT: xxmrghw vs3, v3, v3501; CHECK-P8-NEXT: xxmrglw vs2, v3, v3502; CHECK-P8-NEXT: xvcvspdp vs3, vs3503; CHECK-P8-NEXT: xvcvspdp vs2, vs2504; CHECK-P8-NEXT: xvcvdpuxds v4, vs0505; CHECK-P8-NEXT: xvcvdpuxds v0, vs1506; CHECK-P8-NEXT: xvcvdpuxds v5, vs3507; CHECK-P8-NEXT: xxmrglw vs4, v2, v2508; CHECK-P8-NEXT: xxmrghw vs5, v2, v2509; CHECK-P8-NEXT: xvcvspdp vs4, vs4510; CHECK-P8-NEXT: xvcvspdp vs5, vs5511; CHECK-P8-NEXT: xvcvdpuxds v2, vs4512; CHECK-P8-NEXT: xvcvdpuxds v3, vs5513; CHECK-P8-NEXT: xxswapd vs4, v1514; CHECK-P8-NEXT: stxvd2x vs4, r3, r7515; CHECK-P8-NEXT: xxswapd vs0, v4516; CHECK-P8-NEXT: xvcvdpuxds v4, vs2517; CHECK-P8-NEXT: xxswapd vs1, v0518; CHECK-P8-NEXT: xvcvdpuxds v0, vs6519; CHECK-P8-NEXT: stxvd2x vs0, r3, r4520; CHECK-P8-NEXT: li r4, 96521; CHECK-P8-NEXT: stxvd2x vs1, r3, r4522; CHECK-P8-NEXT: li r4, 80523; CHECK-P8-NEXT: xxswapd vs0, v5524; CHECK-P8-NEXT: stxvd2x vs0, r3, r4525; CHECK-P8-NEXT: li r4, 64526; CHECK-P8-NEXT: xxswapd vs3, v2527; CHECK-P8-NEXT: stxvd2x vs3, r3, r6528; CHECK-P8-NEXT: xxswapd vs1, v3529; CHECK-P8-NEXT: stxvd2x vs1, r3, r5530; CHECK-P8-NEXT: xxswapd vs2, v4531; CHECK-P8-NEXT: xxswapd vs5, v0532; CHECK-P8-NEXT: stxvd2x vs2, r3, r4533; CHECK-P8-NEXT: stxvd2x vs5, 0, r3534; CHECK-P8-NEXT: blr535;536; CHECK-P9-LABEL: test16elt_signed:537; CHECK-P9: # %bb.0: # %entry538; CHECK-P9-NEXT: lxv vs0, 48(r4)539; CHECK-P9-NEXT: lxv vs1, 0(r4)540; CHECK-P9-NEXT: lxv vs3, 16(r4)541; CHECK-P9-NEXT: lxv vs5, 32(r4)542; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1543; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1544; CHECK-P9-NEXT: xxmrglw vs4, vs3, vs3545; CHECK-P9-NEXT: xxmrghw vs3, vs3, vs3546; CHECK-P9-NEXT: xxmrglw vs6, vs5, vs5547; CHECK-P9-NEXT: xxmrghw vs5, vs5, vs5548; CHECK-P9-NEXT: xxmrglw vs7, vs0, vs0549; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0550; CHECK-P9-NEXT: xvcvspdp vs2, vs2551; CHECK-P9-NEXT: xvcvspdp vs1, vs1552; CHECK-P9-NEXT: xvcvspdp vs4, vs4553; CHECK-P9-NEXT: xvcvspdp vs3, vs3554; CHECK-P9-NEXT: xvcvspdp vs6, vs6555; CHECK-P9-NEXT: xvcvspdp vs5, vs5556; CHECK-P9-NEXT: xvcvspdp vs7, vs7557; CHECK-P9-NEXT: xvcvspdp vs0, vs0558; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2559; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1560; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4561; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3562; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6563; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5564; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7565; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0566; CHECK-P9-NEXT: stxv vs0, 112(r3)567; CHECK-P9-NEXT: stxv vs7, 96(r3)568; CHECK-P9-NEXT: stxv vs5, 80(r3)569; CHECK-P9-NEXT: stxv vs6, 64(r3)570; CHECK-P9-NEXT: stxv vs3, 48(r3)571; CHECK-P9-NEXT: stxv vs4, 32(r3)572; CHECK-P9-NEXT: stxv vs1, 16(r3)573; CHECK-P9-NEXT: stxv vs2, 0(r3)574; CHECK-P9-NEXT: blr575;576; CHECK-BE-LABEL: test16elt_signed:577; CHECK-BE: # %bb.0: # %entry578; CHECK-BE-NEXT: lxv vs0, 48(r4)579; CHECK-BE-NEXT: lxv vs1, 0(r4)580; CHECK-BE-NEXT: lxv vs3, 16(r4)581; CHECK-BE-NEXT: lxv vs5, 32(r4)582; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1583; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1584; CHECK-BE-NEXT: xxmrghw vs4, vs3, vs3585; CHECK-BE-NEXT: xxmrglw vs3, vs3, vs3586; CHECK-BE-NEXT: xxmrghw vs6, vs5, vs5587; CHECK-BE-NEXT: xxmrglw vs5, vs5, vs5588; CHECK-BE-NEXT: xxmrghw vs7, vs0, vs0589; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0590; CHECK-BE-NEXT: xvcvspdp vs2, vs2591; CHECK-BE-NEXT: xvcvspdp vs1, vs1592; CHECK-BE-NEXT: xvcvspdp vs4, vs4593; CHECK-BE-NEXT: xvcvspdp vs3, vs3594; CHECK-BE-NEXT: xvcvspdp vs6, vs6595; CHECK-BE-NEXT: xvcvspdp vs5, vs5596; CHECK-BE-NEXT: xvcvspdp vs7, vs7597; CHECK-BE-NEXT: xvcvspdp vs0, vs0598; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2599; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1600; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4601; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3602; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6603; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5604; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7605; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0606; CHECK-BE-NEXT: stxv vs0, 112(r3)607; CHECK-BE-NEXT: stxv vs7, 96(r3)608; CHECK-BE-NEXT: stxv vs5, 80(r3)609; CHECK-BE-NEXT: stxv vs6, 64(r3)610; CHECK-BE-NEXT: stxv vs3, 48(r3)611; CHECK-BE-NEXT: stxv vs4, 32(r3)612; CHECK-BE-NEXT: stxv vs1, 16(r3)613; CHECK-BE-NEXT: stxv vs2, 0(r3)614; CHECK-BE-NEXT: blr615entry:616 %a = load <16 x float>, ptr %0, align 64617 %1 = fptoui <16 x float> %a to <16 x i64>618 store <16 x i64> %1, ptr %agg.result, align 128619 ret void620}621